U.S. Philips Corporation

Robertus W Dekker

Franciscus P Beenker

Aloysius P Thijssen

Rudi J Stans

Max Van Der Star

Joris F Jansen

A method for testing a hierarchically organized integrated circuit means first attacks each assembly in sequence thereof, and in each assembly executing an assembly test cycle. Each assembly test cycle within the assembly in question attacks each macro thereof in sequence and conditionally executes therein a test run under selective control of a macro test mode (MTM) signal. The number of hierarchy levels may be other than three. The method may be applicable to separate integrated circuits or to a wired board with a plurality of circuits.

Method for testing an integrated circuit means having a hierarchical

A method is described, in which a self-test is controlled in a subsystem of a data processing system. Control patterns are transported by the data processing system via a shift register and are then passed to the subsystem via connections used for normal control in the non-testing condition. A characterization of the test result is then loaded again into the shift register via connections also intended for normal use and is subsequently transported by the data processing system. A subsystem suitable for a self-test according to this method is controllable in the self-test condition from a shift register without it being necessary that it is provided with special test connections.

Method of controlling a self-test in a data processing system and data

A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes:

Growing community of inventors

Eindhoven, Netherlands

Robertus W Dekker