Texas Instruments Corporation

Other

Hitachi, Ltd.

Robert Yung-Hsi Tsu

Isamu Asano

William R McKee

Bernard M Kulwicki

Wei-Yung Hsu

Shinpei Iijima

Kenneth D Brennan

Jeffrey A McKee

Qing-Tang Jiang

Scott Robert Summerfelt

Thomas Dyer Bonifield

Howard R Beratan

Chih-Chen Cho

Tsuyoshi Tamaru

Qi-Zhong Hong

Ming J Hwang

Joe W McPherson

Ming-Jang Hwang

Jing Shing Shu

Shintaro Aoyama

Toshio Ando

Masato Kunitomo

Shimpei Iijima

An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layerorof FIGS.-), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer, andof FIGS.and) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (materialof FIGS.and) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.

Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer

The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

Copper transition layer for improving copper interconnection reliability

In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral circuit region

The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode adjacent an insulating region . This base electrode can comprise either polysilicon or a metal. A layer of a first material, such as a siliciding metal, is formed over the base electrode as well as the adjacent insulating region. A self-aligned capacitor electrode can then be formed by reacting the first material with the base electrode and removing unreacted portions of the first material from the insulating region . The capacitor is then completed by forming a dielectric layer over the self-aligned capacitor electrode and a second capacitor electrode over the dielectric layer

Integrated circuit capacitor

An integrated circuit. The circuit includes a memory cell array including wordlines formed on a substrate and bitlines and capacitors formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Integrated circuit and method

A dual damascene process. After the via etch, a via protect layer ( ) is deposited in the via ( ). The via protect layer ( ) comprises a material that has a dry etch rate at least equal to that of the IMD ( ) and a wet etch rate that is approximately 100 times that of the IMD ( ) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern ( ) is formed and both the via protect layer ( ) and IMD ( ) are etched. The remaining portions of the via protect layer ( ) are then removed prior to forming the metal layer ( ).

Yield improvement of dual damascene fabrication through oxide filling

Method of manufacturing a semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity

A semiconductor device and process for making the same are disclosed which incorporate boron, which has been found to be substantially insoluble in BST, into a BST dielectric film,Dielectric film,is preferably disposed between electrodes,and,(which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Boron included in a BST precursor may be used to form boron oxide in a second phase,which is distributed in boundary regions between BST crystals,in film,It is believed that the inclusion of boron allows for BST grains of a desired size to be formed at lower temperature, and also reduces the leakage current of the capacitive structure.

Barium strontium titanate (BST) thin films using boron

The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode,adjacent an insulating region,. This base electrode,can comprise either polysilicon or a metal. A layer,of a first material, such as a siliciding metal, is formed over the base electrode,as well as the adjacent insulating region. A self-aligned capacitor electrode,can then be formed by reacting the first material,with the base electrode,and removing unreacted portions of the first material,from the insulating region,. The capacitor is then completed by forming a dielectric layer,over the self-aligned capacitor electrode,and a second capacitor electrode,over the dielectric layer

A cost-effective method for fabricating MIM capacitors (,). After metal (,) deposition, the metal oxide (,) is formed using an oxidation chemistry that includes CO2 and H2. The CO2/H2 gas ratio is controlled for selective oxidation. Thus, the metal (,) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagent.

Selective oxidation methods for metal oxide deposition on metals in capacitor fabrication

A method of fabricating in-situ doped rough polycrystalline silicon in a single process in a single wafer reactor is disclosed. The method includes substantially simultaneously flowing SiH,, PH,, and H,in the single wafer reactor under predetermined temperature and pressure conditions and gas flow rates that result in nucleation and growth of a rugged polycrystalline silicon.

Method of fabricating in-situ doped rough polycrystalline silicon using a single wafer reactor

Semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity and method of manufacturing same

In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O.sub.2 plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be useful in forming a capacitor 12 dielectric 24. In turn, the capacitor could be used in a DRAM memory device.

Method for fabricating an integrated circuit structure

A method for forming a semiconductor memory device storage cell structure having an increased surface area. The storage cell structure has one or more rough polysilicon surfaces formed by depositing the polysilicon under conditions that result in gas phase dominant nucleation.

Growing community of inventors

Plano, TX, United States of America

Robert Yung-Hsi Tsu