Skyworks Solutions, Inc.

Conexant Systems, Inc.

Raytheon Company

Robert W Warren

Anthony James Lobianco

Nic Rossi

Thomas E Noll

Matthew Sean Read

Anil K Agarwal

Dinhphuoc Vu Hoang

Qing Gan

Steve Xin Liang

Hyun Jung Lee

Hong Shen

Howard E Chen

Larry D Pottebaum

Mark A Kuhlman

Tony LoBianco

Qiuliang Luo

Usama K Abdali

Gene Gan

Suresh Jayaraman

Hyun Jane Lee

Dinphuoc V Hoang

Ravi Ramanathan

Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module includes at least one active device stacked on top of an array of passive surface mount components on a substrate. A conductive or non-conductive adhesive can be used to adhere the active device to the array of passive devices.

3-D stacking of active devices over passive devices

There is provided a system and method for a spot plated leadframe and an IC bond pad via array design for copper wire. There is provided a semiconductor package comprising a leadframe having a pre-plated finish and a spot plating on said pre-plated finish, a semiconductor die including a bond pad on a top surface thereof, and a copper wire bonded to said spot plating and to said bond pad. Optionally, a novel corner via array design may be provided under the bond pad for improved package performance while maintaining the integrity of the copper wire bond. The semiconductor package may provide several advantages including high MSL ratings, simplified assembly cycles, avoidance of tin whisker issues, and low cost compared to conventional packages using gold wire bonds.

Spot plated leadframe and IC bond pad via array design for copper wire

There are provided semiconductor packages having corner pins and methods for their fabrication. Such a semiconductor package includes a leadframe and a die paddle, the leadframe having first and second edge sides meeting to form a first corner. The semiconductor package also includes edge pins arrayed substantially parallel to the first edge side and edge pins arrayed substantially parallel to the second edge side. In addition, the semiconductor package includes a first corner pin situated at the first corner, the first corner pin being electrically isolated from the die paddle.

Semiconductor package with corner pins

According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component.

Methods for fabricating an overmolded semiconductor package with wirebonds for electromagnetic shielding

Overmolded semiconductor package with wirebonds for electromagnetic shielding

An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels.

Semiconductor packages with reduced solder voiding

Wafer level packaging (WLP) packages semiconductor dies onto a wafer structure. After the wafer level package is complete, individual packages are obtained by singulating the wafer level package. The resulting package has a small form factor suitable for miniaturization. Unfortunately conventional WLP have poor heat dissipation. An interposer with a thermal pad can be attached to the semiconductor die to facilitate improved heat dissipation. In one embodiment, the interposer can also provide a wafer substrate for the wafer level package. Furthermore, the interposer can be constructed using well established and inexpensive processes. The thermal pad attached to the interposer can be coupled to the ground plane of a system where heat drawn from the semiconductor die can be dissipated.

Wafer level package with thermal pad for higher power dissipation

There is provided a system and method for a shielded connector module with a molded hood and an LED light pipe. There is provided a shielded connector module comprising a system-in-package (SiP) device having a surface mounted light emitting diode (LED), a metallic shield surrounding the SiP device, a molded hood surrounding the metallic shield, and an LED light pipe in a proximity with the surface mounted LED, the LED light pipe being directed through the metallic shield and the molded hood. By designing the LED light pipe with a concave surface for surrounding the surface mounted LED and by using various techniques to reduce a gap between the LED and the light pipe, light capture and transmission may be optimized for easily viewable high intensity light. A fresnel lens may be optionally attached to the light pipe for wider viewing angles.

Shielded USB connector module with molded hood and LED light pipe

A barrier layer can be attached in a semiconductor package to one or more sensitive devices. The barrier layer can be used to obstruct tampering by a malicious agent attempting to access sensitive information on the sensitive device. The barrier layer can cause the sensitive device to become inoperable if physically tampered. Additional other aspects of the protective packaging provide protection against x-ray and thermal probing as well as chemical and electrical tampering attempts.

Systems and methods of tamper proof packaging of a semiconductor device

Overmolded semiconductor package with a wirebond cage for EMI shielding

A micro electro-mechanical sensor is provided. The micro electro-mechanical sensor includes a substrate, and a conducting plane disposed on the substrate. A conducting via is disposed on the substrate, such as adjacent to the conducting plane. A plurality of ribbon conductors are disposed over the conducting plane and electrically connected to the conducting via, such that the plurality of ribbon conductors form a transducer array in combination with the conducting plane, such as through capacitive coupling that changes in response to changes in the physical shape of the plurality of ribbons.

Micro electro-mechanical sensor (MEMS) fabricated with ribbon wire bonds

In a semiconductor chip, a thermal adhesive is used to bond an internal heat spreader to an active functional die. In an alternative embodiment a dummy die is place directly on top of the active functional die and a thermal adhesive is used to bond an internal heat spreader to the dummy die. This provides a direct and relatively low thermal conductivity path from the heat source, i.e., the functional device to the top of the package, that is, the internal metal heat spreader which is also exposed to the air.

Enhanced thermal dissipation ball grid array package

A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAS devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer.

Growing community of inventors

Newport Beach, CA, United States of America

Robert W Warren