Micrel, Incorporated

Robert W Rumsey

Martin J Alter

Martin E Garnett

Arthur Lam

Hiu Fung Ip

Richard Dolan

Haowei Wu

Hui F Ip

A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

Chip-scale package conversion technique for dies

A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.

Box-in-box field-to-field alignment structure

Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.

Integrating chip scale packaging metallization into integrated circuit die structures

A test structure pattern includes a first comb having a first set of tines, and a second comb having a second set of tines of the same width and spacing as the first set of tines. When the test structure pattern is stepped between fields on a wafer, the first comb and the second comb at least partially overlap on photoresist over a scribe lane between the fields. When the photoresist is developed, the overlap of the first comb and the second comb generates a metal comb. Electrical continuity is checked for the metal tines of the metal comb to determine the misalignment of the fields.

Electrical field alignment vernier

A test structure pattern includes a first comb, a second comb, and a serpentine line. The first comb includes a first set of tines of the same orientation. The second comb includes a second set of tines of the same orientation that are interdigitated with the first set of tines. The serpentine line runs between the interdigitated tines of the first metal comb and the second metal comb. The test structure pattern forms a first metal comb, a second metal comb, and a serpentine metal line on a die. Print quality and resolution is tested by checking for electrical continuity in the serpentine metal line and bridging between the serpentine metal line and one of the first metal comb and the second metal comb.

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Campbell, CA, United States of America

Robert W Rumsey