Hewlett-Packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Hewlett-Packard Company

Xerox Corporation

Qualcomm Incorporated

Saxpy Computer Corporation

Robert S Schreiber

Norman Paul Jouppi

Nathan Lorenzo Binkert

Moray McLaren

Naveen Muralimanohar

Jung Ho Ahn

Doe Hyun Yoon

Paolo Faraboschi

Jichuan Chang

Parthasarathy Ranganathan

Dejan S Milojicic

Mehul A Shah

Raymond G Beausoleil

Marco Fiorentino

Michael S Schlansker

Robert E Tarjan

Shail Aditya Gupta

Jean-Francois C Collard

Qianfan Xu

Indrajit Roy

Alain Darte

William G Horne

Vinod Kumar Kathail

Santosh Abraham

Dhruva Ranjan Chakrabarti

Terence Patrick Kelly

Bantwal R Rau

B Ramakrishna Rau

Hans Boehm

John R Gilbert

Pramod G Joisha

Siddhartha Chatterjee

Shivaram Venkataraman

Prithviraj Banerjee

Gregg Bernard Lesartre

Alan Hersh Karp

Dale Calvin Morris

Harumi Kuno

Boon Seong Ang

Ram Swaminathan

Henry Harlyn Baker

Kimberly Keeton

Alan Lynn Davis

Sheng Li

Kevin T Lim

Charles Stuart Johnson

Alvin AuYoung

Rajeev Balasubramonian

Yunhong Zhou

Nina Mishra

Mukund Sivaraman

Jishen Zhao

Peter Piet

Norm Jouppi

Timothy F Forell

Sudarsun Kannan

Dennis Matthews Wilkinson

Jacob B Leverich

Al Davis

James Hyungsun Park

Gary R Lang

Zeyu Li

Mesut Kuscu

Onkar Patil

Mark C Nicely

A Joel Mannion

Fred J Long

Shang-Hua Teng

Charles F Patton

Terry M Parks

Erik Tamas Bodzsar

Stanko Novakovic

Helen W Cheung

Alina Ene

Nikola Milosavljevic

Anita B Rau

Darren C Conquist

Sadun Anik

Doe-Hyun Yoon

In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.

Graph update flush to a shared memory

A memory controller is to interface with a memory, associated with a plurality of pins, based on a codeword. The codeword is to include a plurality of n-bit symbols. An n-bit symbol of the codeword is to be formed from a plurality of n bursts over time associated with one of the pins of the memory.

Memory controllers to form symbols based on bursts

A high performance computing system that includes a shared fabric memory and a plurality of processors is disclosed. A first processor is coupled to a local storage and executes a first process that, in combination with other processes, causes the plurality of processors to perform certain actions including transferring, from the shared fabric memory to the local storage, a first value corresponding to a first cell of a first set of cells and a first sweep of a stencil code. The actions further include transferring, from a first logical partition in the shared fabric memory associated with the first cell to the local storage, a second value corresponding to a second cell related to the first cell and not in the first set of cells. Further, these actions include updating, by the first process, the first value based on at least the first value and the second value.

Data update of shared fabric memory in a high performance computing system

Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

Memory device write based on mapping

Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint.

Local checkpointing using a multi-level cell

A detector detects, using an error code, an error in data stored in a memory. The detector determines whether the error is uncorrectable using the error code. In response to determining that the error is uncorrectable, an error handler associated with an application is invoked to handle the error in the data by recovering the data to an application-wide consistent state.

Invoking an error handler to handle an uncorrectable error

Write operations on main memory comprise predicting a last write in a dirty cache line. The predicted last write indicates a predicted pattern of the dirty cache line before the dirty cache line is evicted from a cache memory. Further, the predicted pattern is compared with a pattern of original data bits stored in the main memory for identifying changes to be made in the original data bits. Based on the comparison, an optimization operation to be performed on the original data bits is determined. The optimization operation modifies the original data bits based on the predicted pattern of a last write cache line before the last write cache line is evicted from the cache memory.

Performing write operations on main memory

A technique includes generating a checkpoint for an application that is executing on a plurality of nodes of a distributed computing system. Forming the checkpoint includes selectively regulating communication of data from the plurality of nodes to a storage subsystem based at least in part on a replication of the data among the nodes.

Checkpoint generation

According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.

Versioned memory Implementation

Examples of the present disclosure include methods, devices, and/or systems. Identifying network communication patterns can include analyzing a distributed computer program of a network, estimating virtual network communication traffic based on the analysis, and mapping the virtual network communication traffic to a physical network link. Identifying network communications patterns can also include identifying the network communication pattern and categorizing the physical communication network link based on an estimated communication intensity of the mapped communication traffic and the network communication pattern. Identifying network communication patterns can further include optimizing an energy used by the network based on the categorization.

Identifying network communication patterns

A memory device includes a group or block of k-level memory cells, where k&#x3e;2, and where each of the k-level memory cells has k programmable states represented by respective resistance levels.

Representing data using a group of multilevel memory cells

A power management module can select one of a plurality of different operational modes for a hardware component in a computer system based on application performance and total computer system power consumption determined for each of the operational modes.

Computer power management

A sparse array is partitioned into first partitions and a second array is partitioned into second partitions based on an invariant relationship between the sparse array and the second array. The sparse array and the second array are associated with a computation involving the sparse array and the second array. The first partitions and the corresponding second partitions are distributed to workers. A different first partition and corresponding second partition is distributed to each of the workers. Third partitions of the sparse array and corresponding fourth partitions of the second array are determined based on the invariant relationship and measurements of load are received from each of the workers. At least one of the first partitions and the corresponding second partition is different from one of the third partitions and the corresponding fourth partition. The at least one of the first partitions and the corresponding second partition that is different is redistributed among the workers. A different third partition and corresponding fourth partition is executed by each of the workers.

Load-balanced sparse array processing

A method includes selecting a first biclique role in a plurality of roles and finding all roles in the plurality that have a set of vertices of a second type that is a subset of a set of vertices of the second type in the first role; removing each of the subsets from the set of vertices of the second type corresponding to the first role; and reassigning the vertices of the first type to the roles such that original associations between the vertices of the first type and the vertices of the second type are maintained.

Computer-implemented method for role discovery and simplification in access control systems

One embodiment relates to a computer-implemented method for role discovery in access control systems. User accounts are selected according to a predetermined algorithm. For each selected user account, a new role is created covering a set of permissions including all permissions which the user account needs but is not yet covered by another role that the user account has. The new role is given to the user account so that all permissions needed by the user account are covered. Any additional user accounts which still need the set of permissions covered by the new role are also found, and the new role is given to these additional user accounts, if any. Other features, aspects and embodiments are also disclosed.

Computer-implemented method for role discovery in access control systems

Growing community of inventors

Pal Alto, CA, United States of America

Robert S Schreiber