Intel Corporation

Other

Sony Group Corporation

Tahoe Research, Ltd.

Intel Corproation

Intel Corporationn

Google Inc.

Robert S Chau

Jack T Kavalieros

Brian S Doyle

Matthew V Metz

Suman Datta

Mark L Doczy

Marko Radosavljevic

Justin K Brask

Ravi Pillarisetty

Niloy Mukherjee

Gilbert W Dewey

Benjamin Chu-Kung

Uday Shah

Han Wui Then

Sansaptak W Dasgupta

Willy Rachmady

Been-Yih Jin

Seung Hoon Sung

Sanaz Kabehie Gardner

Anand S Murthy

Van H Le

Scott A Hareland

Charles C Kuo

Elijah V Karpov

Kaan Oguz

Niti Goel

Reza Arghavani

Amlan Majumdar

David L Kencke

Mantu K Hudait

Chia-Hong Jan

Chris E Barns

Satyarth Suri

Boyan Boyanov

Patrick R Morrow

Prashant Majhi

Roksana Golizadeh Mojarad

Nancy M Zelick

Markus Kuhn

Leopoldo D Yau

Paul A Packan

Tahir Ghani

Kevin O'Brien

Roza Kotlyar

Valluri Ramana Rao

Dinesh Somasekhar

Annalisa Cappellani

Shaofeng Yu

Kaizad Rumy Mistry

Vivek K De

Rafael Rios

Harold W Kennel

Kimin Jun

Ebrahim Andideh

Nick Lindert

Brian E Roberds

Justin Brockman

Mitchell C Taylor

John P Barnak

Dmitri E Nikonov

Paul B Fischer

James M Blackwell

Titash Rakshit

Peter G Tolchinsky

Mohamad A Shaheen

Bruce E Beattie

James M Powers

Simon Yang

Mark T Bohr

Stephen M Cea

Aaron D Lilak

Gerhard Schrom

Hui Jae Yoo

Christopher J Jezewski

Ali Keshavarzi

Scott Bruce Clendenning

Anh Phan

Sey-Shing Sun

David B Fraser

Kenneth C Cadien

Eric R Dickey

Timothy E Glassman

Tristan A Tronic

Jose A Maiz

Kari Härkönen

Ying Zhou

Johanna M Swan

Adel A Elsherbini

Ian A Young

Valery M Dubin

Nicole K Thomas

Shigeki Tomishima

Wilfred Gomes

Mark Y Liu

Martin D Giles

Chunlin Liang

Steven J Keating

Jack Hwang

Lawrence D Wong

Anne E Miller

A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

Non-planar gate all-around device and method of fabrication thereof

Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

Gallium nitride (GAN) three-dimensional integrated circuit technology

A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Method for fabricating transistor with thinned channel

A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

Metallization structures for stacked device connectivity and their methods of fabrication

System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Fand also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits

Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.

Gallium nitride (GaN) transistor structures on a substrate

III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

III-N epitaxial device structures on free standing silicon mesas

III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

Resistive memory cells and precursors thereof, methods of making the same, and devices including the same

Techniques are disclosed for forming group III material-nitride (III-N) microelectromechanical systems (MEMS) structures on a group IV substrate, such as a silicon, silicon germanium, or germanium substrate. In some cases, the techniques include forming a III-N layer on the substrate and optionally on shallow trench isolation (STI) material, and then releasing the III-N layer by etching to form a free portion of the III-N layer suspended over the substrate. The techniques may include, for example, using a wet etch process that selectively etches the substrate and/or STI material, but does not etch the III-N material (or etches the III-N material at a substantially slower rate). Piezoresistive elements can be formed on the III-N layer to, for example, detect vibrations or deflection in the free/suspended portion of the III-N layer. Accordingly, MEMS sensors can be formed using the techniques, such as accelerometers, gyroscopes, and pressure sensors, for example.

Group III-N MEMS structures on a group IV substrate

An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.

Low stray field magnetic memory

An embodiment includes an apparatus including: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, including a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.

Perpendicular magnetic memory with symmetric fixed layers

Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Growing community of inventors

Beaverton, OR, United States of America

Robert S Chau