Texas Instruments Corporation

Robert R Doering

Luigi Colombo

Archana Venugopal

Benjamin Stassen Cook

Clarence W Teng

Bing W Shen

William F Richardson

Gregory J Armstrong

James Cooper Wainerdi

Ashwin H Shah

Arup Polley

David A Baglee

Christopher Slawinski

Donald J Redwine

John Paul Tellkamp

Dirk N Anderson

Ih-Chin Chen

Gordon P Pollack

William R Hunter

Michael P Duane

Mark Bordelon

A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.

Semicondctor device package thermal conduit

An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

Thermal routing trench by additive processing

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

High thermal conductivity vias by additive processing

Semiconductor device package thermal conduit

An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.

Integrated circuit nanoparticle thermal routing structure in interconnect region

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

Interconnect via with grown graphitic material

An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

Integrated circuit nanoparticle thermal routing structure over interconnect region

A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.

Graphene heterolayers for electronic applications

Graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.

Low noise graphene hall sensors, systems and methods of making and using same

A Graphene Hall sensor (GHS) is provided with a modulated gate bias signal in which the modulated gate bias signal alternates at a modulation frequency between a first voltage that produces a first conductivity state in the GHS and a second voltage that produces approximately a same second conductivity state in the GHS. A bias current is provided through a first axis of the GHS. A resultant output voltage signal is provided across a second axis of the Hall sensor that includes a modulated Hall voltage and an offset voltage, in which the Hall voltage is modulated at the modulation frequency. An amplitude of the Hall voltage that does not include the offset voltage is extracted from the resultant output voltage signal.

Low-offset Graphene Hall sensor

An integrated circuit includes an interconnect which includes a metal layer, a layer of graphene on at least one of the top surface of the interconnect or the bottom surface of the interconnect, and a layer of hexagonal boron nitride (hBN) on the layer of graphene, opposite from the metal layer. Dielectric material of the integrated circuit contacts the layer of hBN. The layer of graphene has one or more atomic layers of graphene. The layer of hBN is one to three atomic layers thick. The interconnect may have a lower graphene layer on the bottom surface of the metal layer with a lower hBN layer, and an upper graphene layer on the top surface of the metal layer, with an upper hBN layer.

Heterostructure interconnects for high frequency applications

A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a dipole-inducing magnetic field which induces magnetic dipoles in the SWNTs so that a strength of a dipole depends on a conductivity of the SWNT containing the dipole, orienting the metallic SWNTs, and exposing the SWNTs to a magnetic field with a spatial gradient so that the oriented metallic SWNTs drift in the magnetic field gradient and thereby becomes spatially separated from the semiconducting SWNTs. An apparatus for the process of sorting SWNTs is disclosed.

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Plano, TX, United States of America

Robert R Doering