Microchip Technology Inc.

Robert P Ma

Neil F Deutscher

Roger D St Amand

Justin Sato

Donald S Gerber

Greg Stom

Walter Lundy

Brian Dee Hennes

Walter E Lundy

Brian Hennes

Justin H Sato

A method for manufacturing a semiconductor die may have the steps of:&#x2014;Providing a semiconductor substrate;&#x2014;Processing the substrate to a point where shallow trench isolation (STI) can be formed;&#x2014;Depositing at least one underlayer having a predefined thickness on the wafer;&#x2014;Depositing a masking layer on top of the underlayer;&#x2014;Shaping the masking layer to have areas of predefined depths;&#x2014;Applying a photolithograthy process to expose all the areas where the trenches are to be formed; and&#x2014;Etching the wafer to form silicon trenches wherein the depth of a trench depends on the location with respect to the masking layer area.

Method for manufacturing a semiconductor die with multiple depth shallow trench isolation

A merged two transistor memory cell of an EEPROM, and method of fabricating same, is provided. The memory cell includes a substrate and insulating layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes an ONO stack film that is disposed between the floating gate and the shared gate. In fabricating the memory, the ONO stack film is formed adjacent to the top and side surfaces of the floating gate. The ONO stack film is also formed so as not to be interposed between a potion of the shared gate that is adjacent to the substrate and the insulating layer.

Memory cell having an ONO film with an ONO sidewall and method of fabricating same

A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.

Method of forming side dielectrically isolated semiconductor devices and

A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin oxynitride lateral diffusion barrier to oxygen is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate.

Method of forming narrow thermal silicon dioxide side isolation regions

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Phoenix, AZ, United States of America

Robert P Ma