International Business Machines Corporation

Globalfoundries Inc.

Robert Mark Rassel

Douglas Duane Coolbaugh

Xuefeng Liu

Ebenezer E Eshun

Zhong-Xiang He

Anthony K Stamper

Jeffrey Bowman Johnson

Steven H Voldman

Richard A Phelps

David Charles Sheridan

Alvin Jose Joseph

Yun Shi

David S Collins

Bradley Alan Orner

Michael Joseph Zierak

Anil Kumar Chinthakindi

Jeffrey P Gambino

Alan Bernard Botula

Mark E Stidham

Edmund Juris Sprogis

Richard John Rassel

Peter James Lindgren

Kunal Vaed

Keith Edward Downes

Douglas Brian Hershberger

Terence B Hook

William Joseph Murphy

Renata A Camillo-Castillo

Daniel Scott Vanslette

Stephen Scott Furkay

Frederick Gustav Anderson

Xiaowei Tian

Heidi L Greer

Daniel C Edelstein

John J Ellis-Monaghan

Kai D Feng

Stephen Arthur St Onge

Kevin N Ogg

John Edward Florkey

Seong-dong Kim

Kangguo Cheng

Steven M Shank

Qizhi Liu

James Stuart Dunn

James Spiros Nakos

John B Campi, Jr

Louis DeWolf Lanzerotti

Francis Roger White

Richard L Rassel

Erik Mattias Dahlstrom

Timothy Wayne Kemerer

Edward J Nowak

Robert J Gauthier, Jr

Sebastian Theodore Ventrone

Vibhor Jain

Ping-Chuan Wang

Kirk David Peterson

Mark David Jaffe

Chandrasekharan Kothandaraman

Herbert Lei Ho

Robert K Leidy

John Joseph Pekarik

David Louis Harame

Alain F Loiseau

James Albert Slinkman

William F Clark, Jr

Robert Allen Groves

Vidhya Ramachandran

Andreas Daniel Stricker

Natalie Barbara Feilchenfeld

Kenneth Jay Stein

Deok-Kee Kim

Hongwen Yan

John Matthew Safran

Dan Moy

Ephrem G Gebreselasie

Yves T Ngu

Kimball M Watson

Mete Erturk

Panglijen Candra

Norman Whitelaw Robson

Michael J Hauser

Nicholas Theodore Schmidt

Eric Thompson

Alan D Norris

Jenifer E Lary

John J Benoit

Edward Jack Gordon

Michael Lawrence Gautsch

Xudong Wang

Kristin M Ackerson

Alan Frederick Norris

Thomas Kessler

Yan Ding

Jeffrey P Bonn

Brent A Goplen

Brian L Kinsman

Xuefeng Lie

Bradley A Omer

Zhong-Xiang Ile

In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias

Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

Integrated circuit and design structure having reduced through silicon via-induced stress

A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Forming structures on resistive substrates

Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

Si and SiGeC on a buried oxide layer on a substrate

An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure

Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure

A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Method of making heat sink for integrated circuit devices

Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process.

Schottky barrier diodes with a guard ring formed by selective epitaxy

A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Silicided trench contact to buried conductive layer

Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

Back-end-of-line metal-oxide-semiconductor varactors

An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first set of trenches formed in a first surface of the substrate; a second set of trenches formed in a second surface of the substrate; and at least one through silicon via connecting the first set of trenches and the second set of trenches.

Semiconductor device including in wafer inductors, related method and design structure

A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce R. A related method and design structure are also disclosed.

Asymmetric wedge JFET, related method and design structure

Growing community of inventors

Colchester, VT, United States of America

Robert Mark Rassel