Intel Corporation

Robert M Nickerson

Robert L Sankman

Purushotham Kaushik Muthur Srinath

Brian Taggart

Omkar G Karhade

Debendra Mallik

Nicholas Randolph Watts

Shripad Gokhale

Russell K Mortensen

Sanka Ganesan

Rajasekaran Swaminathan

Mitul Bharat Modi

Edward Rudolph Prack

Sri Chaitra J Chavali

Ronald L Spreitzer

Shawna M Liff

Nitin A Deshpande

Sairam Agraharam

Amruthavalli Pallavi Alur

Christopher L Rumer

Sandeep Razdan

Nisha Ananthakrishnan

Amram Eitan

Shan Zhong

Elizabeth Nofen

Hsin-Yu Li

John Decker

Yang Guo

John C Conner

Nick Ross

Rees Winters

Chia-Pin Chiu

John Stephen Guzek

Leonel R Arana

Charles A Gealer

Nicholas Holmberg

Zhaozhi Li

Andrew V Mazur

Denis Myasishchev

Xiaorong Xiong

Linda Zhang

Eric Jin Li

Ram S Viswanath

Yoshihiro Tomita

Javier Soto Gonzalez

Chandra Mohan Jha

Charan K Gurumurthy

Pramod Malatkar

Zhimin Wan

Yosuke Kanaoka

Charavana K Gurumurthy

Thomas J De Bonis

Javier Soto

Dale A Hackitt

Edward W Jaeck

Haifa Hariri

Prasanna Raghavan

Hamid Ekhlassi

Huiyang Fei

Naga Sivakumar Yagnamurthy

Min Tao

Kumar Abhishek Singh

Thomas J Debonis

Lesley A Polka

Nazmiye Acikgoz Akbay

Fadi Y Hafez

Hai Ding

Ronald I Spreitzer

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

Through mold interconnect drill feature

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.

Laser ablation-based surface property modification and contamination removal

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone

Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Offset interposers for large-bottom packages and large-die package-on-package structures

Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.

Micro-trenching mold interface in a pop package

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 &#x3bc;m, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.

Thermally coupled package-on-package semiconductor packages

Growing community of inventors

Chandler, AZ, United States of America

Robert M Nickerson