Dialog Semiconductor (uk) Limited

Robert Lamoon

Jesus Mennen Belonio, Jr

Rajesh Subraya Aiyandra

Ernesto Gutierrez, Iii

Ian Kent

Habeeb Mohiuddin Mohammed

Domingo Jr Maggay

A wafer level chip scale package is described. At least one redistribution layer is connected to a wafer through an opening through a first polymer layer to a metal pad on a top surface of the wafer wherein the redistribution layer has a roughened top surface and wherein holes are formed through the at least one redistribution layer in an area where the redistribution layer has an area exceeding 0.2 mm. At least one UBM layer contacts the at least one redistribution layer through an opening in a second polymer layer wherein the second polymer layer contacts the first polymer layer within the holes promoting cohesion between the first and second polymer layers and wherein the roughened top surface promotes adhesion between the at least one redistribution layer and the second polymer layer.

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Portishead, United Kingdom

Robert Lamoon