Texas Instruments Corporation

Robert L Virkus

David B Spratt

Eldon J Zorinsky

Robert H Eklund

Kenneth E Bean

Richard L Yeakley

Hoang H Hoang

Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions. The collector contact region is self aligned to the second sidewall oxide spacer which prevents the contact of base and heavily doped collector. Finally, the oxide cap covering the upper emitter surfaces is removed and emitter, base and collector contact regions are silicided to reduce contact resistance.

Method of forming a recessed contact bipolar transistor

Method of forming a recessed contact bipolar transistor and field effect

A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of the base contact (34) to define a second reference edge (42). An emitter well (44) and a collector well (46) are then defined on either side of the contact with the vertical wall of the emitter well (44) aligned with the reference edge (42). A dopant material is then disposed adjacent the reference edge (42) and the dopant diffused into the substrate from a lateral direction to form a P-type base region (58) with a graded impurity profile. N-doped regions (64) and (66) are then formed in the emitter and collector wells to form the emitter and collector of the transistor.

Method for forming a horizontal self-aligned transistor

An advanced electromigration resistant lead (34) is formed over an insulator layer (36). The lead (34) is processed from a metallic film having a known grain size. A rapid thermal anneal is conducted to increase the grain size and to reduce the number of triple points. The lead (34) is also engineered to have rounded edges (40) rather than sharp edges. The rounded edges (40) reduce the amount of stress in the lead (34) and help further reduce the effects of electromigration.

Advanced electromigration resistant interconnect structure and process

Method for forming a recessed contact bipolar transistor and field

A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

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Dallas, TX, United States of America

Robert L Virkus