Intel Corporation

Robert L Sankman

Debendra Mallik

Ravindranath Vithal Mahajan

Sanka Ganesan

John Stephen Guzek

Amruthavalli Pallavi Alur

Johanna M Swan

Robert Alan May

Islam A Salama

Shawna M Liff

Qing Ma

Sri Ranga Sai Boyapati

Dheeraj R Subbareddy

Md Altaf Hossain

Ankireddy Nalamalpu

Robert Starkston

Srinivas V Pietambaram

Feras Eid

Sairam Agraharam

Aleksandar Aleksov

Chia-Pin Chiu

Kristof Darmawikarta

Zhichao Zhang

William J Lambert

David Gregory Figueroa

Pooya Tadayon

Eric Jin Li

Ram S Viswanath

Weng Hong Teh

Sri Chaitra Jyotsna Chavali

Adel A Elsherbini

Valluri Ramana Rao

Rahul N Manepalli

Robert M Nickerson

Chandra Mohan Jha

Sandeep B Sane

Telesphor Kamgaing

Mark T Bohr

Kemal Aygun

Gregg William Baeckler

Omkar G Karhade

Zhiguo Qian

Wilfred Gomes

Yoshihiro Tomita

Mitul Bharat Modi

Pramod Malatkar

Rajat Agarwal

Yuan-Liang Li

Ravi Prakash Gutala

Scott J Weber

Rajesh Kumar

Quan Anh Tran

Yikang Deng

Aravind Raghavendra Dasu

Sheng C Li

Hong Xie

Edward Rudolph Prack

Tarek A Ibrahim

Xavier Francois Brun

Sriram Srinivasan

Sandeep Razdan

Marko Radosavljevic

Ian A Young

Sujit Sharan

Dmitri E Nikonov

Kevin Lai Lin

Mathew J Manusharow

Mihir K Roy

Jiangqi He

Kaladhar Radhakrishnan

Nachiket R Raravikar

James Chris Matayabas, Jr

Krishna Bharath

Javier Soto Gonzalez

Brandon M Rawlings

Jianyong Xie

Suddhasattwa Nad

Thorsten Meyer

Patrick R Morrow

Sasha N Oster

Paul B Fischer

Min Suet Lim

Nitin A Deshpande

Eng Huat Goh

Bernd Waidhas

Khang Choong Yong

Yonggang Li

Gerald Ofner

Joshua Heppner

Je-Young Chang

Thomas Wagner

Rajasekaran Swaminathan

Thomas Dory

Dilan Seneviratne

Gang Duan

Ravi V Mahajan

Ravi S Prasher

Edvin Cetegen

Christopher L Rumer

Rajendra C Dias

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

Planar integrated circuit package interconnects

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Interconnect architecture with silicon interposer and EMIB

Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Semiconductor device stack-up with bulk substrate material to mitigate hot spots

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.

Substrateless double-sided embedded multi-die interconnect bridge

An inductor can be formed in a coreless electronic substrate, such that the fabrication process does not result in the magnetic material used in the inductor leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming conductive vias with a lithographic process, rather than a standard laser process, in combination with panel planarization to prevent exposure of the magnetic material to the plating and/or etching solutions/chemistries.

Coreless electronic substrates having embedded inductors

A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

Inorganic-based embedded-die layers for modular semiconductive devices

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Heterogeneous nested interposer package for IC chips

Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die. The semiconductor package further includes an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.

Embedded die architecture and method of making

A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

Programmable logic device with fine-grained disaggregation

An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

Multi-chip packaging

Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

EMIB patch on glass laminate substrate

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

Multi-die ultrafine pitch patch architecture of interconnect bridge over glass layer and method of making

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Microelectronic device with embedded die substrate on interposer

Growing community of inventors

Phoenix, AZ, United States of America

Robert L Sankman