Freescale Semiconductor,inc.

Nxp Usa, Inc.

Robert Joseph Wenzel

George R Leal

Marc Alan Mangrum

Jie-Hua Zhao

Edward R Prack

David G Wontor

Brian D Sawyer

Kevin John Hess

Chu-Chung Lee

Victor Adrian Chiriac

Tien Yu T Lee

Owen R Fay

Michael B Vincent

Jinbang Tang

Tingdong Zhou

Peter R Harper

Scott K Pozder

Craig S Amrine

Darrel R Frear

James S Golab

David Clegg

Lizabeth Ann Keser

Trung Duong

Stanley Andrew Cejka

Ilan Lidsky

Matthew A Ruston

David M Wells

A semiconductor device having a radiating element and a directing structure is provided. The semiconductor device includes a device package. A semiconductor die is coupled to the radiating element integrated in the device package. The directing structure is affixed to the device package by way of an adhesive. The directing structure is located over the radiating element and configured for propagation of radio frequency (RF) signals.

Semiconductor device with directing structure and method therefor

A semiconductor device includes a package substrate, a semiconductor die attached to a first major surface of the package substrate, and a plurality of wire bonds attached between the semiconductor die and the first major surface of the package substrate. The device further includes a conductive plate over the semiconductor die, plurality of wire bonds, and package substrate wherein a first major surface of the conductive plate faces the first major surface of the package substrate. The device further includes a plurality of conductive extensions attached to the first major surface of the conductive plate, wherein each conductive extension extends from the first major surface of the conductive plate and between two adjacent wire bonds of the plurality of wire bonds.

Methods and devices with enhanced grounding and shielding for wire bond structures

Embodiments of an interconnect structure are provided, the interconnect structure including: a reference plane structure having a first major surface and a second major surface opposite the first major surface, the reference plane structure including a plurality of through holes from the first major surface to the second major surface; a plurality of conductive columns, each conductive column centered within a through hole; and a plurality of isolation structures, each isolation structure fills an annular region within the through hole between each conductive column and surrounding portion of the reference plane structure.

Package to board interconnect structure with built-in reference plane structure

A substrate having an edge; a first and second active trace, wherein the first active trace corresponds to a first signal of a differential pair and the second active trace corresponds to a second signal of the differential pair; and a first and second conductive via which are located at different distances from the edge. The first active trace is routed to the first conductive via, and the second active trace is routed around the first conductive via to the second conductive via such that the second active trace is between the first conductive via and the edge. The substrate includes a first plating trace in electrical contact with the first active trace, and a second plating trace in electrical contact with the second active trace, wherein the first and second plating traces are routed to the edge on different metal layers of the substrate.

Substrate with routing

A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

Packaged integrated circuit using wire bonds

A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Circuit device with at least partial packaging and method for forming

A package assemblyincludes a semiconductor die (e.g., an RF power amplifier)fixed within the cavity of a conductive leadframeusing a thermally and electrically-conductive adhesive material. The semiconductor diehas a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e.g., a copper leadframe)has two planar surfaces and a cavity formed therein. The adhesive materialis configured to couple the semiconductor diewithin the cavity of the conductive leadframesuch that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.

Methods and apparatus for a semiconductor device package with improved thermal performance

A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads.

Semiconductor die with die pad pattern

A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP.

Integrated circuit module with integrated passive device

A method that locates a plurality of die for forming a plurality of packaged integrated circuits. A frame is placed over the support structure, wherein the frame includes a plurality of openings therein and each opening of the plurality of openings has at least two walls. Each die of a plurality of die is placed over the support structure, wherein each die has at least two adjacent edges. The relative placing of the frame and the die results in each die being in an opening of the plurality of openings. Encapsulant is applied to the plurality of die. Either or both of the plurality of die and frame are moved in relation to the other in a manner that causes the two adjacent edges of each die of the plurality of die to substantially abut to and align with the two walls of an opening of the plurality of openings.

Die positioning for packaged integrated circuits

A method of packaging a semiconductor includes providing a support structure. An adhesive layer is formed overlying the support structure and is in contact with the support structure. A plurality of semiconductor die is placed on the adhesive layer. The semiconductor die are laterally separated from each other and have electrical contacts that are in contact with the adhesive layer. A layer of encapsulating material is formed overlying and between the plurality of semiconductor die and has a distribution of filler material. A concentration of the filler material is increased in all areas laterally adjacent each of the plurality of semiconductor die.

Method of packaging semiconductor devices

A semiconductor device includes a semiconductor die having a plurality of contact pad sites, a plurality of contact pads, an encapsulant barrier, and an encapsulant. A plurality of contact pads is in electrical contact with a predetermined corresponding different one of the contact pad sites. An encapsulant barrier is positioned at an outer perimeter of the semiconductor die. The encapsulant barrier has a height that is as high as or greater than a highest of the plurality of contact pads. The encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites. An encapsulant surrounds the semiconductor die and one side of the encapsulant barrier. The encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the device is encapsulated while being supported by a temporary base support layer.

Semiconductor device with a protected active die region and method therefor

A method of forming an embedded device build-up package () includes forming a first plurality of features () over a packaging substrate (), wherein the first plurality of features () comprises a first feature and a second feature, forming at least a first crack arrest feature () in a first crack arrest available region (), wherein the first crack arrest available region is between the first feature and the second feature, forming a second plurality of features () over the first plurality of features () wherein the second plurality of features includes a third feature and a fourth feature, and forming at least a second crack arrest feature () in a second crack arrest available region (), wherein the second crack arrest feature () is between the third feature and the fourth feature, and the second crack arrest feature () is substantially orthogonal to the first crack arrest feature ().

Method of forming crack arrest features in embedded device build-up package and package thereof

Fine pitch contacts are achieved by using traces that extend to the contacts without requiring capture pads at the contact pads. Capture pads are desirably avoided because they have a diameter greater than the line to which they are attached. Preferably, adjacent contact pads are present in the same opening in the dielectric. The traces to the contact pads are in a line so that no widening is required where the lines make contact to the contact pads. The lines can be widened before they get to the contact pads but at the contact pads, they are substantially at the minimum width for the line. Thus, the contact pads can be at a pitch much lower than if capture pads were used.

Fine pitch interconnect and method of making

A multi-layer structure () includes a first build-up layer structure () configured to connect to a heat-generating module (), a second build-up layer structure () configured to connect to a substrate, and a middle layer () provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component () and a heat spreader (). A first set of thermal vias () extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.

Growing community of inventors

Austin, TX, United States of America

Robert Joseph Wenzel