Mentor Graphics Corporation

Other

Robert John Bloor

Hans Erich Multhaup

William Eugene Jacobus

Ashraf Mohamed Salem

Mohamed Abdelsalam Ahmed Hassan

Khaled Salah Mohamed

Mahmoud Mohamed Ali

Duaine Wright Pryor, Jr

Aspects of the disclosed technology relate to techniques for protocol analysis during a circuit design verification process. A protocol-specific message capture unit captures messages while or after being transmitted over one or more communication channels between a circuit design model and one or more target devices. A protocol-independent interface unit receives signals carrying the messages and information for processing the messages from the protocol-specific message capture unit. After processing the messages, the protocol-independent interface unit sends the messages to an analysis unit for analyzing the messages based on a protocol file. The analysis unit may then output the messages for displaying.

Generic protocol analyzer for circuit design verification

A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to supply a sector status value for each memory sector of the memory which is changed to a value equal to the memory status value when a write operation is performed on the each memory sector of the memory; and third circuitry configured to supply, when a read operation is performed on a memory sector of the memory, a value stored in the memory sector as output of the read operation if the sector status value for the memory sector is equal to the memory status value or a predefined value as the output of the read operation in other situations.

Full memory logical erase for circuit verification

A disclosed interface between an emulator and a network that is readily scalable. In one aspect, a scalable solution is achieved through a hardware interface board positioned between the network and the emulator to allow proper transfer there between. A computer is separated from and coupled to the hardware interface board and provides the necessary control signals. Because it is done in hardware separated from the computer, the interface board is readily scalable through the simple addition of network chip sets. In another aspect, the interface board can be placed in two modes of operation, a live test mode and a direct test mode. In yet another aspect, packet formats may be changed on the interface board so that it appears to the emulator as if the network is operating at a different data transfer speed than is actually the case.

Hardware interface board for connecting an emulator to a network

An hardware emulation environment is disclosed wherein software execution is accelerated by switching memory and/or peripheral and clock implementation from the hardware emulator toga faster running processor board coupled to the hardware emulator. A switch is positioned between the hardware emulator and a processor running on the processor board. A design block implemented on a dedicated resource, such as memory or a peripheral, is located on the processor board and is designed to functionally mimic a design block modelled in programmable resources in the hardware emulator. In one embodiment, a user selectively configures a switch to accelerate the software execution by choosing a trigger event, such as a memory range or a software breakpoint. Upon detecting the trigger event, the switch switches the clock and/or bus routing so that the processor communicates directly with the design block on the processor board, rather than with a functionally equivalent design block in the hardware emulator. The processor also is clocked using a faster clock allowing the acceleration of the software execution.

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Hertfordshire, United Kingdom

Robert John Bloor