International Business Machines Corporation

Fairchild Semiconductor Corporation

Samsung Electronics Co., Ltd.

Robert J Purtell

Keith Kwong Hon Wong

Christian Lavoie

Kenneth John McCullough

Yun Yu Wang

Kirk David Peterson

Yun-Yu Wang

Qizhi Liu

Cyril Cabral, Jr

Marwan H Khater

Wayne Martin Moreau

Randy William Mann

Andreas Daniel Stricker

Charles Jesse Taft

John Patrick Simons

Paul David Agnello

Roy Arthur Carruthers

Ronnen Andrew Roy

Peter John Geiss

James McKell Edwin Harper

Jae-Sung Rieh

Jean Louise Jordan-Sweet

John Michael Cotte

Keith Randal Pope

BethAnn Rainey

Anita Madan

William Alfred Syverson

Bradley Paul Jones

Laura Beth Rothman

Jin-Jwang Wu

Bruce Bennett Doris

Haining S Yang

Renee Tong Mo

Omer H Dokumaci

Henry K Utomo

Wesley Charles Natzle

Kwong Hon Wong

Anthony Gene Domenicucci

Ying Li

James J Murphy

Sadanand Vinayak Deshpande

Beth Ann Rainey

Kevin E Mello

Catherine Ivers

Jun-Keun Kwak

Steve Sapp

Semiconductor devices and methods for making such devices are described. The UMOS semiconductor devices contain single-crystal gates that have been re-grown or formed at low temperature using microwaves. The devices can be formed by providing a semiconductor substrate, forming a trench in the substrate, forming an insulating layer in the trench, depositing a pre-gate layer on the insulating layer, the pre-gate layer comprising a conductive and/or semiconductive material (Si or SiGe) with a non-single crystal structure, contacting the pre-gate layer with a seed layer with a single-crystal structure, and heating the pre-gate layer using microwaves at low temperatures to recrystallize the non-single crystal structure into a single-crystal structure. These processes can improve the resistance and mobility of the gate either as a single crystal structure, optionally with a silicide contact above the source-well junction, enabling a higher switching speed UMOS device. Other embodiments are described.

Single crystal U-MOS gates using microwave crystal regrowth

Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dielectric layers that have been deposited and/or flowed by the application of microwave energy ('MW dielectric layers'). The dielectric layers can be made by providing a substrate in a reaction chamber, flowing a precursor gas mixture (containing atoms that react to form a dielectric material) in the reaction chamber, and then subjecting the gas mixture to microwave energy at a frequency and power density sufficient to cause the atoms of the precursor gas mixture to react and deposit to form a dielectric layer on the substrate. As well, the devices can be made by applying microwave energy to an already-deposited dielectric film at a frequency and power density sufficient to cause the atoms of the deposited dielectric material to flow. Using microwave energy permits the dielectric layer to be formed using low temperature processing, providing several benefits to the semiconductor device along with process flow efficiency and low cost. Other embodiments are described.

Low temperature dielectric flow using microwaves

A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

Method and apparatus for forming nickel silicide with low defect density in FET devices

A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.

Structure and method for forming a salicide on the gate electrode of a trench-gate FET

Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

Methods of base formation in a BiCOMS process

Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging.

Air break for improved silicide formation with composite caps

A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400&#xb0; C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.

Method for improved formation of nickel silicide contacts in semiconductor devices

The present invention provides a method of fabricating semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSi). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSi) into a second phase (MSi) with x&#x3c;y. The metal silicide conversion causes either volumetric shrinkage or expansion in the S/D metal silicide layers of the FET, which in turn generates intrinsic tensile or compressive stress in the S/D metal silicide layers under confinement by the silicon nitride layer.

Methods for forming CMOS devices with intrinsically stressed metal silicide layers

A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400&#xb0; C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in time when the semiconductor wafer has cooled to temperature range of about 275-300&#xb0; C., depositing a cap layer over the cobalt layer, and annealing the semiconductor wafer so as to create silicide contacts at portions on the wafer where cobalt is formed over silicon.

Method for improved formation of cobalt silicide contacts in semiconductor devices

A method and apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

Methods of base formation in a BiCMOS process

A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.

Clustered surface preparation for silicide and metal contacts

A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.

Method for reducing dendrite formation in nickel silicon salicide processes

Growing community of inventors

Mohegan Lake, NY, United States of America

Robert J Purtell