Motorola Corporation

Robert J Mattox

Syd R Wilson

Steven J Fong

Andrew G Nagy

Frederick J Robinson

James A Sellers

Paul R Proctor

A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.

Method of forming substrate contact trenches and isolation trenches

A structure and method for forming an isolation wall in an etched trench are described. The trench walls are covered by a thin silicon oxide layer and the trench conformally filled with an oxy-nitride mixture having a particular range of composition so as to produce a neutral to slight tensile stress in the oxy-nitride relative to silicon. The structure is very simple to fabricate and creates fewer defects in the silicon substrate than prior art techniques. Buried voids in the filled trench are eliminated.

Method for forming a dielectric filled trench

A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer is formed over a bottom interconnect layer, and an interlayer dielectric is formed on the sacrificial layer. A via is etched in the interlayer dielectric, exposing the sacrificial layer. The sacrificial layer is isotropically etched to expose an area of the interconnect metal that is larger than the area of the via and a via metallization is selectively formed on the interconnect metal by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer, is filled with the via metallization, thereby providing a contact area to the bottom interconnect metal which is larger than the via metallization itself.

Process for making a multilayer metallization structure

Trench isolation process and structure

A method for the construction of submicron features using optical lithography technology. A material is deposited on a surface to be etched, this material is partially etched through using optical lithography technology. Sidewalls are deposited to reduce the size of this etched area to the submicron size desired. The etch of the layer is then completed resulting in a submicron mask for the substrate below.

Method for obtaining submicron features from optical lithography

A method is described for forming dielectric filled isolation trenches in semiconductor substrates in which a differentially etchable etch-stop layer is provided above the surface of the substrate during the trench filling process so that the height of the trench filling relative to the surface of the substrate may be adjusted for optimum overall results during subsequent fabrication steps and so that the substrate surface may be protected from contact with the etching reagents used during planarization of the trench filling material. This avoids damage to the substrate surface and permits improved surface planarity.

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Tempe, AZ, United States of America

Robert J Mattox