Cray Research, Inc.

Other

Cray Research Systems, Inc.

Chippewa Data Control LLC

Robert J Halford

The present disclosure relates to novel and advantageous systems and methods of processing and managing data in critical or large-scale systems, such as airliner, automobile, space station, power plant, and healthcare systems. Particularly, the present disclosure relates to a rules-driven data and control method mapped onto complementary physical architecture for a more reliable operational system. By maintaining an algebraic encoding of control and application data at fine granularities, whether static or in transit, it is possible to detect, isolate, and correct many errors that would otherwise go undetected. This more dynamic and precise method addresses cases where deteriorating conditions or cataclysmic events affect much of the system simultaneously, including the control system itself.

Method and architecture for critical systems utilizing multi-centric orthogonal topology and pervasive rules-driven data and control encoding

The invention discloses a data validation, mirroring and error/erasure correction method for the dispersal and protection of one and two-dimensional data at the micro level for computer, communication and storage systems. Each of 256 possible 8-bit data bytes are mirrored with a unique 8-bit ECC byte. The ECC enables 8-bit burst and 4-bit random error detection plus 2-bit random error correction for each encoded data byte. With the data byte and ECC byte configured into a 4 bit&#xd7;4 bit codeword array and dispersed in either row, column or both dimensions the method can perform dual 4-bit row and column erasure recovery. It is shown that for each codeword there are 12 possible combinations of row and column elements called couplets capable of mirroring the data byte. These byte level micro-mirrors outperform conventional mirroring in that each byte and its ECC mirror can self-detect and self-correct random errors and can recover all dual erasure combinations over four elements. Encoding at the byte quanta level maximizes application flexibility. Also disclosed are fast encode, decode and reconstruction methods via boolean logic, processor instructions and software table look-up with the intent to run at line and application speeds. The new error control method can augment ARQ algorithms and bring resiliency to system fabrics including routers and links previously limited to the recovery of transient errors. Image storage and storage over arrays of static devices can benefit from the two-dimensional capabilities. Applications with critical data integrity requirements can utilize the method for end-to-end protection and validation. An extra ECC byte per codeword extends both the resiliency and dimensionality.

Multi-dimensional data protection and mirroring method for micro level data

A modular input-output subsystem for a supercomputer is disclosed. Peripheral devices are coupled to the system through channel adaptor interfaces, while communication with the CPU is through high speed data channels. A memory buffer is provided to buffer data transfers between the peripherals and the Central Processing Units (CPUs) and the Solid State Storage Devices (SSDs).

Modular input/output system for supercomputers

The present invention discloses an error recovery method for parallel architecture data storage devices. The present invention provides means for simultaneously arranging data on a plurality of recording surfaces so that intermittent and/or solid failures do not prevent access to the data stored thereon. A first error correcting code comprising a parity bit is generated for each dataword. The dataword and the parity bit are stored simultaneously and bit-wise to a plurality of recording surfaces. A second error correcting code is generated for a plurality of bits transmitted to a specific recording surface. The second error correcting code is written onto the same recording surface as the bits from which it was generated. The second error correcting code is used to detect and correct intermittent errors in the data read from a particular recording surface. The first error correcting code is used to correct data read from a particular surface when the second error correcting code indicates that a solid failure has occurred, which the second error correcting code cannot correct. The result is a data storage device combining large capacity and fast transfer rates with improved fault tolerance.

Error recovery method and apparatus for high performance disk drives

A multiple disk drive array storage device is described which emulates the operation of a single disk drive so that the handshaking and protocol between the array storage device and the host computer appears to the host computer to be that of a single disk drive. The array storage device includes a plurality of individual disk drives, each of which having its spindle synchronized to the other disk drives using a master clock synchronization. Digital data words are received by the array storage device controller which divides the words into subparts and writes each subpart to a different disk drive within the storage device. The buffering and formatting of the digital data for reading and writing from the individual disk drives is accomplished by the controller transparent to the host computer.

Single disk emulation interface for an array of synchronous spindle disk

A peripheral interface system is disclosed. An input-output processor is provided to receive input-output commands from a central processing unit. Up to four multiplexing units may be connected to the input-output processor, with each multiplexing unit providing an interface for up to four controller units, which may be used to control a peripheral device. The multiplexing unit includes a pair of data buffers, each with its own addressing circuit, and each functionally divided into four storage areas, each storage area providing four registers to store four parcels of data. Data is transferred between the input-output processor and the controller units by filing the storage area in a buffer from the local memory of the input-output processor in a serial fashion over a DMA channel provided between the multiplexer and the local memory. Data transferred from the storage area in the multiplexer to a controller is sent one parcel every four clock periods, according to a scanner/time slot synchronization scheme between the multiplexer and the up to four controllers which may be connected thereto. Similarly, data parcels are transferred from the controller to the multiplexer on a scanner/time slot basis, and from the storage area of the multiplexer to the memory in a serial, consecutive fashion over the DMA channel. In operation, the buffers of the multiplexer are alternately filled and emptied such that one may be filling while the other one is emptying. A pair of buffers are also provided in the controller unit, which also may be alternately filled and emptied as between the peripheral device and the multiplexer.

Peripheral interface system

An electrical interface system provides a set of signals to be used in transferring information between first and second terminals. To transfer information from the first terminal to the second terminal, a WRITE CLOCK, FUNCTION/DATA READY, four CODE, one CODE PARITY, 16 DATA and DATA PARITY signals are provided. To transfer information from a second terminal to the first terminal, a READ CLOCK, STATUS/DATA READY, ERROR, DONE, INDEX/SECTOR MARK, STATUS PARITY, 16 DATA and one DATA PARITY signals are provided. The four CODE signals may be formed to signal any one of a plurality of requested functions to the second terminal, while the second terminal may indicate its general status to the first terminal with the ERROR, DONE, READY and MARK signals, each terminal capable of further defining functions or status by formation of words with the data signals. Protocol for transferring information between the terminals is provided, and provides that a predetermined plurality of data parcels be transferred in response to each request for data on consecutive cycles of the WRITE CLOCK or READ CLOCK signals. The system further provides that the process of transferring said predetermined plurality of parcels is automatically repeated a second predetermined number of times in order that an entire data record be transferred between the terminals in response to a READ or WRITE request. The system further provides for particular sequencing of signals and communication of information between the terminals using combinations of interfacing signals.

Growing community of inventors

Chippewa Falls, WI, United States of America

Robert J Halford