Novellus Systems Incorporated

University of California

The United States of America As Represented by the United States

Other

International Business Machines Corporation

Robert J Contolini

Jonathan David Reid

Evan E Patton

Steven T Mayer

Eliot K Broadbent

Anthony F Bernhardt

Jeffrey D Morse

John Owen Dukovic

Edward C Opocensky

Steve Taatjes

Steven W Taatjes

Jingbin Feng

Anthony M McCarthy

Ronald G Musket

Lisa A Tarte

Andrew J McCutcheon

Wayne L Bonde

John Stephen Drewery

John D Porter

Paul G Carey

Richard N Hill

Vincent Malba

Jon Reid

Alain Harrus

Vladimir Liberman

James M Yoshiyama

Robert A Riddle

Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.

Method and apparatus for potential controlled electroplating of fine patterns on semiconductor wafers

In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.

Dynamically variable field shaping element

A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.

Electroplating process chamber and method with pre-wetting and rinsing capability

The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.

Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation

An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.

Membrane partition system for plating of wafers

Apparatus for potential controlled electroplating of fine patterns on semiconductor wafers

Method for potential controlled electroplating of fine patterns on semiconductor wafers

An electrochemical reactor is used to electrofill damascene architecture for integrated circuits or for electropolishing magnetic disks. An inflatable bladder is used to screen the applied field during electroplating operations to compensate for potential drop along the radius of a wafer. The bladder establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film seed layer of copper on the wafer.

Adjustable flange for plating and electropolishing thickness profile control

An electrochemical reactor is used to electrofill damascene architecture for integrated circuits. A shield is used to screen the applied field during electroplating operations to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film seed layer of copper on the wafer.

Method and apparatus for uniform electroplating of integrated circuits using a variable field shaping element

A disclosed electroplanarization process involves &ldquo;masking&rdquo; certain regions of a wafer surface during electropolishing. The regions chosen for masking are features of relatively low aspect ratio (i.e., features that are wider than they are deep). The masking is accomplished with a material of relatively low ionic conductivity, which effectively slows or blocks transport of the metal ions produced during electropolishing. Examples of masking materials include concentrated phosphoric acid and certain polymers.

Electroplanarization of large and small damascene features using diffusion barriers and electropolishing

A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO,), silicon nitride (SiN,), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.

Adhesion layer for etching of tracks in nuclear trackable materials

Electroplating process including pre-wetting and rinsing

An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.

Electric potential shaping apparatus for holding a semiconductor wafer during electroplating

A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called 'terminal effect', the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.

Growing community of inventors

Lake Oswego, OR, United States of America

Robert J Contolini