Texas Instruments Corporation

Novellus Systems Incorporated

Other

Robert H Havemann

Robert H Eklund

Girish Anant Dixit

Shin-Puu Jeng

Qi-Zhong Hong

Bruce E Gnade

Chih-Chen Cho

Richard A Stoltz

Leo Stroth

Wei-Yung Hsu

Manoj K Jain

Sang-Hyeob Lee

James A Fair

Carole D Graas

Richard S Hill

Willibrordus Gerardus Maria Van Den Hoek

Anthony J Konecni

Nerissa Taylor

David A Bell

Glenn B Alers

Mary Anne Plano

Jungwan Sung

Mark Stephen Rodder

Jeffrey Alan West

Jiong-Ping Lu

Che-Chia Wei

Roger A Haken

Justin F Gaynor

Kenneth E Bean

Gordon P Pollack

Thomas E Tang

Vernon R Porter

Eden M Zielinski

Stephen W Russell

Samuel C Baber

Paul E Brunemeier

Andrew P Lane

Archita Sengupta

Larry A Hahn

Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for this deposition process without adding footprint in the semiconductor fabrication plant.

Nanoparticle cap layer

In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.

Integrated circuit having a doped porous dielectric and method of manufacturing the same

A method for creating a refractory metal and refractory metal nitride cap effective for reducing copper electromigration and copper diffusion is described. The method includes depositing a refractory metal nucleation layer and nitriding at least the upper portion of the refractory metal layer to form a refractory metal nitride. Methods to reduce and clean the copper lines before refractory metal deposition are also described. Methods to form a thicker refractory metal layer using bulk deposition are also described.

Selective refractory metal and nitride capping

Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a pre-formed layer of semiconductor to produce a porous semiconductor layer.

Method of fabricating low dielectric constant dielectric films

A composition comprises a first component that provides a predetermined response to radiation, and a second component. Upon curing of the composition, portions of the first component bind together portions of the second component to form an inhomogeneous material having physical properties substantially determined by the second component. The function provided by the first component's response to radiation and the macroscopic properties determined by the second component are largely decoupled and thus may be separately optimized. Some embodiments provide photo-patternable low dielectric constant materials that may be advantageously employed in metal interconnect layers in integrated circuits, for example.

Inhomogeneous materials having physical properties decoupled from desired functions

Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a preformed layer of semiconductor to produce a porous semiconductor layer.

According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches. The conductor is electrically coupled to the conductive liner. The method also includes covering the portion of the conductive liner overlying the platform after lining the surface. The method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.

Methods for forming a fuse in a semiconductor device

A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300&deg; C., and preferably between about 20&deg;-275&deg; C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;< 3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100&deg;-300&deg; C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Low pressure, low temperature, semiconductor gap filling process

An interconnect structure having refractory sidewalls for enhanced yield, performance and reliability. The primary purpose of the refractory metal is to getter sidewall impurities, residual polymers, and corrosive species by-products from the plasma etch and cleanup processes used to pattern interconnects. In a preferred embodiment, the refractory metal reacts with the conducting layer to form an intermetallic which further enhances the endurance of the metallization against stress-induced rupturing and via-induced electromigration. The disclosed structures and methods are particularly advantageous in &ldquo;zero-overlap&rdquo; designs, and aggressive pitch patterns where linewidth and corrosion control are critical, but are also advantageous in &ldquo;Damascene&rdquo; pattern definition applications.

Surface modified interconnects

Method of making horizontal bipolar transistor with insulated base structure

A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.

Transistor and method

A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

Integrated circuit interconnect and method

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Garland, TX, United States of America

Robert H Havemann