Juniper Networks, Inc.

Telefonaktiebolaget Lm Ericsson (publ)

Intel Corporation

Azul Systems, Inc.

Robert G Hathaway

Nazar A Zaidi

Ricardo Ramirez

David T Hass

Ramesh Panwar

Frederick R Gruner

Elango Ganesan

Fred Gruner

Mark Bryers

Stephan G Meier

Michael Freed

Abbas Rashid

Yen C Lee

Sankar Ramanoorthi

Mark Vilas

John Phillips

Gregory G Spurrier

Yuhong Zhou

Evan Gewirtz

Kevin B Normoyle

Edward Ho

Chau Anh Ngoc Nguyen

Ramesh K Panwar

Jose Niell

Brian Alleyne

David A Kruckemyer

Michael Feng

Edmund C Chen

John Gregory Favor

Jack H Choquette

Daniel Christian Biederman

Ranjit Joseph Rozario

Amit Kumar

Ronen Chayat

Alain Gravel

Edmund G Chen

Matthew James Webb

Chih-Jen Chang

Wing Cheung

Brad Burres

Eric Trehus

Yaw Fann

Nadav Turbovich

Todd D Basso

Chau Ahn Ngoc Nguyen

Ramesh Penwar

Jayaram Beladakere

Ricky See

Amit Y Kumar

A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.

Processor related communications

Technologies for processing network packets in an agent-mesh architecture include a network interface controller (NIC) of a computing device configured to write, by a network fabric interface of a memory fabric of the NIC, a received network packet to the memory fabric in a distributed fashion. The network fabric interface is configured to send an event message indicating the received network packet to a packet processor communicatively coupled to the memory fabric. The packet processor is configured to read, in response to having received the generated event message, at least a portion of the received network packet from the memory fabric, identify an agent of the NIC for additional processing of the received network packet, generate a network packet received event message indicating the received network packet is available for processing, and transmit the network packet received event message to the identified agent. Other embodiments are described herein.

Technologies for processing network packets in agent-mesh architectures

A method for packet job scheduler in data processing based on workload self-learning is disclosed. In response to receiving an incoming packet, the packet processor checks workload usage of an isolation group (IG) associated with the incoming packet, the IG being a classification of packets defined for the purpose of processing the incoming packet. The packet processor then determines whether the workload usage of the IG associated with the incoming packet exceeds a predetermined threshold. In response to the workload usage of the IG associated with the incoming packet not exceeding the predetermined threshold, the packet processor forwards the incoming packet to be executed by a packet execution unit, and then it updates the workload usage of the IG associated with the incoming packet based on execution of the incoming packet by the packet execution unit.

Method and system for packet job scheduler in data processing based on workload self-learning

A method for processing data packets in a pipeline and executed by a network processor. The pipeline includes a plurality of logical blocks, each logical block configured to process one stage of the pipeline. Each data packet includes a descriptor and a data. The network processor is coupled to a resource for storing the data. The method reduces latency and enables non-blocking processing of data packets by forwarding a unique identification of a write request from a first logical block to a subsequent second logical block in the pipeline, the write request to modify the data in the resource. The method includes receiving the descriptor for processing at the first logical block, generating the write request and the unique identification for the write request, transmitting the write request to the resource, and transmitting the unique identification towards the second logical block before an acknowledgement is returned by the resource.

Acknowledgement forwarding

Methods and apparatus for pseudo-random hardware resource allocation through a plurality of hardware elements. In an embodiment, resource list entries are configured to each identify one hardware element of the plurality of hardware elements. Index list entries are configured to each identify one resource list entry. An index list pointer is set to identify a first index list entry of the plurality of index list entries, and hardware resources are requested from a first hardware element of the plurality of hardware elements by identifying, using the index list pointer, the first index list entry; identifying, using the first index list entry, a first resource list entry; selecting the hardware element identified by the first resource list entry as the first hardware element; and sending a request for hardware resources to the first hardware element.

Pseudo-random hardware resource allocation through the plurality of resource controller based on non-repeating sequence of index list entries

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Content service aggregation system

A request for reading data from a memory location of a main memory is received, the memory location being identified by a physical memory address. In response to the request, a cache memory is accessed based on the physical memory address to determine whether the cache memory contains the data being requested. The data associated with the request is returned from the cache memory without accessing the memory location if there is a cache hit. The data associated is returned from the main memory if there is a cache miss. In response to the cache miss, it is determined whether there have been a number of accesses within a predetermined period of time. A cache entry is allocated from the cache memory to cache the data if there have been a predetermined number of accesses within the predetermined period of time.

Method and apparatus for accessing cache memory

A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.

Digital counter segmented into short and long access time memory

A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

Digital processor for processing long and short pointers and converting each between a common format

A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.

Explicitly regioned memory organization in a network element

A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.

Subsystem and method for encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use in a 76-bit memory module

A command is received from a first agent via a first predetermined memory-mapped register, the first agent being one of multiple agents representing software processes, each being executed by one of processor cores of a network processor in a network element. A first queue associated with the command is identified based on the first predetermined memory-mapped register. A pointer is atomically read from a first hardware-based queue state register associated with the first queue. Data is atomically accessed at a memory location of the memory based on the pointer. The pointer stored in the first hardware-based queue state register is atomically updated, including incrementing the pointer of the first hardware-based queue state register, reading a queue size of the queue from a first hardware-based configuration register associated with the first queue, and wrapping around the pointer if the pointer reaches an end of the first queue based on the queue size.

Programmable queue structures for multiprocessors

Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module

Growing community of inventors

Santa Clara, CA, United States of America

Robert G Hathaway