Mosaid Technologies Corporation

Mosaid, Inc.

Robert F Harland

Peter B Gillingham

Richard C Foss

Valerie L Lines

Atsushi Wada

Masami Mitsuhashi

Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense nodes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.

Dynamic random access memory using imperfect isolating transistors

A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vthrough the transistors. The boosting capacitors are charge by V. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

DRAM boosted voltage supply

A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V . Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by V through the transistors. The boosting capacitors are charge by V . A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Dynamic random access memory boosted voltage supply

Boosted voltage supply

A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V,. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V,as in the prior art. The boosting capacitors are charged by V,, thus eliminating drift tracking problems associated with clock boosting sources and V,. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

High voltage boosted word line supply charge pump and regulator for DRAM

A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

High voltage boosted word line supply charge pump and regulator for dram

A DRAM having a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low resistance power supply conductors extending in parallel with the row for carrying logic high level and logic low level voltages, sense amplifier enabling signal conductors extending across the chip accessible to the sense amplifiers, apparatus for coupling sense inputs of the sense amplifiers to the power supply conductors, and apparatus coupling the sense amplifier enabling signal conductors to the apparatus for coupling sense inputs, for enabling passage of current resulting from the logic high level and low level voltages to the sense amplifiers.

Method for DRAM sensing current control

A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating draft tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

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Carp, Canada

Robert F Harland