Synopsys, Inc.

Hewlett-packard Company

Agilent Technologies, Inc.

Robert E Gleason

Kit M Cham

Xin Zhou

Yaogang Lian

Linyong Pang

Thomas Christopher Cecil

Guangming Xiao

John F McCarty

A technique for determining a set of calibration parameters for use in a model of a photo-lithographic process is described. In this calibration technique, images of a test pattern that was produced using the photo-lithographic process are used to determine corresponding sets of calibration parameters. These images are associated with at least three different focal planes in an optical system, such as a photo-lithographic system that implements the photo-lithographic process. Moreover, an interpolation function is determined using the sets of calibration parameters. This interpolation function can be used to determine calibration parameters at an arbitrary focal plane in the photo-lithographic system for use in simulations of the photolithographic process, where the set of calibration parameters are used in a set of transmission cross coefficients in the model of the photo-lithographic process.

Determining calibration parameters for a lithographic process

A technique for determining a full-field Mask Error Enhancement Function (MEEF) associated with a mask pattern for use in a photo-lithographic process is described. In this technique, simulated wafer patterns corresponding to the mask pattern are generated at an image plane in an optical path associated with the photo-lithographic process. Then, the full-field MEEF is determined. This full-field MEEF includes MEEF values in multiple directions at positions along one or more contours that define boundaries of one or more features in the one or more simulated wafer patterns. Moreover, at least one of the MEEF values is at a position on a contour where a critical dimension for a feature associated with the contour is undefined.

Full-field mask error enhancement function

A technique for determining a set of calibration parameters for use in a model of a photo-lithographic process is described. In this calibration technique, images of a test pattern that was produced using the photo-lithographic process are used to determine corresponding sets of calibration parameters. These images are associated with at least three different focal planes in an optical system, such as a photo-lithographic system that implements the photo-lithographic process. Moreover, an interpolation function is determined using the sets of calibration parameters. This interpolation function can be used to determine calibration parameters at an arbitrary focal plane in the photo-lithographic system for use in simulations of the photo-lithographic process, where the set of calibration parameters are used in a set of transmission cross coefficients in the model of the photo-lithographic process.

An active matrix pixel within an active matrix display includes a photodiode that is optically connected to a light emitting diode within the pixel in order to detect a portion of the luminous flux that is generated by the light emitting diode. The photodiode discharges excess charge within the pixel in response to the detected portion of luminous flux. Once the excess charge is discharged, the light emitting diode stops emitting light. In an embodiment, the gate of a drive transistor is controlled by the charge on a storage node. If the charge on the storage node sets a voltage that exceeds the threshold voltage of the drive transistor then the drive transistor conducts. The amount of charge on the storage node above that which is needed to set the threshold voltage is referred to as the excess charge.

Active matrix light emitting diode display

A novel BICMOS output buffer is taught including circuit means for firstly discharging the bases of the bipolar pull up and bipolar pull down transistors, and secondly to connect the base of an output transistor to its emitter when that output transistor is conducting, thereby insuring maximum voltage swing of the output voltage. The circuit means comprises an MOS transistor for discharging the base of an output transistor, and a depletion mode MOS transistor for connecting the base of an output transistor to its emitter. By utilizing MOS and depletion mode transistors, a significant area advantage is achieved, particularly when the MOS and depletion mode transistors are merged.

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San Carlos, CA, United States of America

Robert E Gleason