Tokyo Electron Limited

Air Products and Chemicals, Inc.

International Business Machines Corporation

Tokyo Electron Limi Ted

Toyko Electron Limited

Soitec

Robert Daniel Clark

Kandabara N Tapily

Gerrit J Leusink

Kai-Hung Yu

Jeffrey Smith

Cory Wajda

Angelique Denise Raley

Arthur Kenneth Hochberg

Steven Consiglio

Mark I Gardner

H Jim Fulford

David L O'Meara

Nicholas Joy

Dina Triyoso

Gyanaranjan Pattanaik

Qiang Zhao

Richard Farrell

Soo Doo Chae

Ian Colgan

Henan Zhang

David Hurley

Takahiro Hakamata

Sophie Thibaut

Ying Trickett

Jason Mehigan

Vijay Narayanan

Hemanth Jagannathan

Lars W Liebmann

Anton J deVillers

Hiroaki Niimi

Daniel Chanemougame

Christian Dussarrat

Chantal Arena

Barry P Linder

Paul Charles Jamison

Christiaan J Werkhoven

Charles Michael Birtcher

Mirko Vukovic

Kaoru Maekawa

Ronald W Nasman

Thomas Andrew Steidl

Eric Chih-Fang Liu

Lior Huli

Lisa F Edge

Gert J Leusink

Marinus Hopstaken

Yun Han

Vincent M Omarjee

Rodney Lee Robison

Glenn Kuchenbeiser

Paul T Gutwin

Lars-Ake Ragnarsson

Mihaela Ioana Popovici

Shan Hu

Shihsheng Chang

Kirk Scott Cuthill

Ioan Domsa

Hareesh Thridandam

Corey Lemley

Barry Clarke

Sangita Kumari

Peter Delia

Gerhardus Van Der Linde

Patrick Hughes

Maciej Burel

Richard J Dunning

Venkat Pallem

Shintaro Aoyama

John D Loftin

A method of processing a substrate that includes: loading the substrate having a raised feature with at least two sidewalls exposed in a processing chamber; depositing a first layer over the substrate to cover a first portion of the two sidewalls; depositing a second layer over the first layer to cover a second portion of the two sidewalls; depositing a third layer over the second layer and the raised feature to cover a third portion of the sidewalls and a top surface of the raised feature; performing an anisotropic dry etching that removes portions of the second layer and the third layer, a remainder of the second layer forming a second sidewall spacer and a remainder of the third layer forming a third sidewall spacer; and performing an isotropic etching that selectively removes the second sidewall spacer to expose portions of the sidewalls of the raised feature.

Method of forming 3-dimensional spacer

A method of processing a substrate that includes: loading the substrate in a processing chamber, the substrate including a raised feature of a semiconductor; forming a conformal dopant layer on the raised feature by atomic layer deposition (ALD); forming a metal layer over the raised feature; thermally treating the dopant layer to form an ultra-shallow dopant region in the raised feature by diffusion of a dopant from the dopant layer into the raised feature; and thermally treating the metal layer to form an ohmic contact region in the raised feature by diffusion of a metal from the metal layer into the raised feature.

Ultra-shallow dopant and ohmic contact regions by solid state diffusion

A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.

Selective film formation using a self-assembled monolayer

A method of processing a substrate that includes forming over the substrate an extreme ultraviolet (EUV)-active photoresist film including a network of metal oxide terminated with alkoxy groups and patterning the EUV-active photoresist film with EUV lithography.

EUV active films for EUV lithography

A process for forming a semiconductor package is disclosed. The process includes providing a first substrate including a first dielectric layer. The process includes overlaying a first surface of the first dielectric layer with a first bonding layer that includes aluminum. The process includes providing a second substrate including a second dielectric layer. The process includes overlaying a second surface of the second dielectric layer with a second bonding layer that includes alkoxy-siloxide. The process includes forming a third bonding layer by combining the first bonding layer and the second bonding layer so as to bond the first substrate to the second substrate.

Bonding layer and process of making

A backside reveal method includes providing a semiconductor material substrate, depositing an epitaxial high-k etch stop layer on the semiconductor material substrate, forming an integrated circuit device layer on the epitaxial high-k etch stop layer, and attaching a carrier substrate to a front side of the integrated circuit device layer. The method further includes removing a portion of a thickness of the semiconductor material substrate to leave a remaining portion of the thickness of the semiconductor material substrate, removing, by a first selective etching, the remaining portion of the semiconductor material substrate, and removing, by a second selective etching, the epitaxial high-k etch stop layer to expose a backside of the integrated circuit device layer. The epitaxial high-k etch stop layer has good lattice match and high etch selectivity relative to the semiconductor material substrate.

Epitaxial high-K etch stop layer for backside reveal integration

Methods for the manufacture of semiconductor devices with integrated two-dimensional (2D) materials are disclosed. Aspects can include forming a base structure comprising a seed material with a chemical element; forming source/drain contacts coupled to first and second portions of the base structure, respectively, wherein the source/drain contacts each have at least the chemical element; exposing a third portion of the base structure; selectively growing a 2D material at least coupled to the third portion of the base structure; and forming an active gate coupled to the 2D material.

Replacement channel 2D material integration

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Method for filling recessed features in semiconductor devices with a low-resistivity metal

A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.

Semiconductor manufacturing platform with in-situ electrical bias and methods thereof

In certain embodiments, a method for designing a semiconductor device includes generating a 2D design for fabricating chiplets on a substrate. The chiplets are component levels for a multi-chip integrated circuit. The 2D design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The first and second chiplets are adjacent on the substrate. The second layout is a mirror image of the first layout across a reference line shared by the first and second chiplets. The first surfaces of the first and second chiplets are both either top or bottom surfaces. The method further includes generating one or more photomasks according to the design.

Facilitating alignment of stacked chiplets

Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material formed within features (e.g., trenches, holes, slits, etc.), and on more planar areas of a patterned substrate, when a critical dimension (CD) of the features is relatively small compared to the more planar areas of the patterned substrate. In the present disclosure, uniform wet etching is provided by ensuring that wall surfaces adjacent to the material being etched exhibit a neutral surface charge when exposed to the etch solution used to etch the material.

Methods to prevent surface charge induced cd-dependent etching of material formed within features on a patterned substrate

A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.

Transistor stack of vertical channel ferroelectric FETs and methods of forming the transistor stack

Ground cover board

A semiconductor device and method of forming. The semiconductor device contains microelectronic components embedded in a single crystalline dielectric material. The method of forming a semiconductor device includes providing a single crystalline substrate, epitaxially depositing a single crystalline dielectric material on the single crystalline substrate, and forming microelectronic components in the single crystalline dielectric material. The single crystalline dielectric material can contain carbon with a diamond structure or hexagonal boron nitride (h-BN) with a graphene structure.

Crystalline dielectric systems for interconnect circuit manufacturing

Systems and methods for manufacturing two-dimensional (2D) gas channel for vertical transistors. The system can include a semiconductor device. The semiconductor device can include a channel structure surrounding a first dielectric core. The channel structure can include a first two-dimensional (2D) material and a second 2D material. The semiconductor device can include a source metal surrounding a first portion of the channel structure. The semiconductor device can include a drain metal surrounding a second portion of the channel structure. The semiconductor device can include a gate metal surrounding a third portion of the channel structure.

Semiconductor device having channel structure with 2D material

Growing community of inventors

Livermore, CA, United States of America

Robert Daniel Clark