Micron Technology Incorporated

Robert D Patraw

John A Smythe

Jigish D Trivedi

Michael A Walker

Kevin L Beaman

Keith R Cook

M Ceredig Roberts

Gurtej S Sandhu

Martin Ceredig Roberts

First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material. The spin-on-dielectric is densified within the second isolation trench.

Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry

A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

Liner for shallow trench isolation

Methods for forming shallow trench isolation

The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry

The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode. The method still further comprises depositing a dielectric layer on the at least one isolated lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.

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Boise, ID, United States of America

Robert D Patraw