International Business Machines Corporation

Robert Charles Dockerty

Shakir A Abbas

Sudipta Kumar Ray

Gordon J Robbins

Ciro Neal Ramirez

Ronald Maurice Fraga

Narasipur G Anantha

Francisco H De La Moneda

Michael R Poponiak

Paul L Garbarino

Charles Levern Reynolds, Jr

Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.

Column grid array substrate attachment with heat sink stress relief

Supporting structure for a ball grid array surface mounted integrated circuit device composed of support solder formed at selective corner locations on the ball grid array surface of the integrated circuit device. In one form, L-shaped patterns of high melting temperature solder are formed along the axes defined by the ball grid array and are characterized in that cross sections of the L-shaped pattern match that of the solder balls along one axis, and represent a continuum of solder between solder ball locations along the other axis. Support solder can be added where necessary to provide both structural reinforcement and thermal conduction. Control of the cross section of the support solder ensures that surface tension effects of the molten low temperature reflow solder used to connect the integrated circuit device does not materially change the final relative spacing between the integrated circuit device balls and the underlying printed circuit board contacts.

Structurally reinforced ball grid array semiconductor package and systems

A method for fabricating a semiconductor integrated circuit structure having sub-micrometer gate length field effect transistor devices is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. A first insulating layer such as silicon dioxide which is designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a conductive layer, a second silicon dioxide layer, a first silicon nitride layer, a polycrystalline silicon layer and a second nitride layer are formed thereover. The multilayer structure is etched to result in a patterned polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A well controlled sub-micrometer thickness layer is formed on these vertical sidewalls by thermal oxidation of the polycrystalline silicon surfaces. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness silicon dioxide sidewall layer portions of which extend across certain of the device regions. The sidewall layer is utilized as a mask in etching the first silicon nitride layer, the second silicon dioxide layer and the conductive layer to form the gate electrode of the field effect transistor devices in the conductive layer having the length of the sidewall coating. Ion implantation is then accomplished adjacent to the gate electrode to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide, polycide (a combination of layers of polycrystalline silicon and metal silicide) or the like.

MOSFET Structure and process to form micrometer long source/drain spacing

A method for fabricating a semiconductor integrated circuit structure having a sub-micrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. These semiconductor regions are designated to contain devices. At least one layer is formed over the device designated regions and etched to result in a patterned layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness sidewall layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness sidewall layer portions of which extend across certain of the device regions. The desired pattern of PN junctions are now formed in the substrate using for example diffusion or ion implantation techniques with the controlled thickness sub-micrometer layer used as a mask. The effect is the transfer of the submicron pattern into underlying region. This method is particularly useful in forming a sub-micrometer length gate electrode of a field effect transistor.

Sub-micrometer channel length field effect transistor process

Electrical contacts to diffused regions in a semiconductor substrate are made by a process which reduces the space needed in memory or logic cell layouts. The contacts are made such that they overlap, but are insulated from, adjacent conductors. The contacts are formed in a manner which avoids shorting of the diffused junctions to adjacent structures without being limited by lithographic overlay tolerances.

Borderless diffusion contact process and structure

An improved field effect transistor structure which reduces a leakage phenomenon, termed the 'sidewalk' effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

Field effect transistor structure and method for making same

An improved field effect transistor structure which reduces a leakage phenomenon, termed the 'sidewalk' effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

Field effect transistor structure and method of making same

A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or off-chip drivers or can be utilized for analog circuitry.

Process for making field effect and bipolar transistors on the same

A non-volatile memory cell that includes a Schottky barrier diode, located over a sub-diffused line or region formed within the substrate, acting as the control element. Information is stored in the device by introducing electrons into a nitride-oxide interface located at the perimeter of the Schottky barrier junction. Thus, the injected electrons are subject to trapping in the nitride-oxide layer, causing depletion in the epi region adjoining the diode interface, thereby influencing the current carrying state of the device.

Non-volatile Schottky barrier diode memory cell

A Schottky barrier diode having an encircling floating polycrystalline silicon gate which becomes charged upon avalanche breakdown of the diode. The gate is self-aligned with respect to the Schottky barrier diode metal so that the gate uniformly overhangs the depletion area in the semiconductor when the diode is reverse biased. The gate is insulated from the semiconductor material and from the metal by dielectric layers including silicon dioxide and silicon nitride.

Schottky barrier diode having chargeable floating gate

A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current. The cell includes spaced source and drain regions, a gate dielectric layer capable of trapping a charge, a substrate contact electrode; a means to induce a trapped charge into the gate dielectric layer, including a means to apply a voltage larger than the threshold voltage to the gate electrode to form an inversion layer, and a means to apply a voltage to the drain electrode causing channel current to flow; a means to remove the trapped charge, including a means to apply a voltage equal to or exceeding the avalanche voltage to the drain to cause avalanching; a means to determine the presence or absence of a charge in the gate dielectric including a means to apply a voltage to the gate which is larger than the threshold voltage and a voltage to the drain that is significantly less than the avalanche voltage, and a means to determine the substrate current.

Non-volatile memory cell and array using substrate current

A process for forming holes with precisely controlled dimension and position in monocrystalline silicon wafers wherein the holes are fabricated with vertical sides. In the preferred process, both sides of the silicon body are masked, opposite registered openings made in the masking layers, an impurity introduced through the openings into the body forming low resistivity regions, the body anodically etched through the openings until a porous silicon region is formed completely through the body, and subsequently removing the resultant porous silicon region with a silicon etchant.

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Highland, NY, United States of America

Robert Charles Dockerty