Amkor Electronics, Inc.

Teijin Limited

Amkor Technology, Inc.

Robert C Marrs

Tadashi Hirakawa

Ronald J Molnar

An interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate are formed. To form the interconnection, a metallization is formed on each of the substrate bonding contacts. Metal ball bond bumps are formed on selective ones of the bonding pads and then coined. The substrate and integrated circuit chip are heated. The coined ball bond bumps are then placed into contact with the corresponding metallizations, pressure and ultrasonic energy are applied, and a metal-to-metal bond is formed between each coined ball bond bump and the corresponding metallization.

Integrated circuit chip to substrate interconnection

Integrated circuit chip to substrate interconnection and method

A packaged semiconductor die includes a heat sink having a locking feature that interlocks with the encapsulant encapsulating the die to minimize or eliminate delamination of the encapsulant from the heat sink. A surface of the heat sink can be exposed to the exterior of the encapsulant. The invention applies broadly to packaged integrated circuits including multichip modules and hybrid circuits, as well as to packaged transistors. In one embodiment of the invention, a locking moat has a cross-sectional shape that has, at a first distance beneath a locking surface of the heat sink, a width that is larger than a width at a second distance beneath the locking surface, the second distance being smaller than the first distance. The locking moat can have, for example, a 'keyhole' cross-sectional shape or a circular cross-sectional shape. The locking moat can be formed by, for example, stamping or chemical etching. In another embodiment of the invention, the locking feature is a locking region. The locking region can be, for example, a plurality of dimples or deep holes formed by, for instance, stamping, grinding, mechanical or laser drilling, or chemical etching, a roughened area formed by abrading or selective electroplating, or a patterned region formed by coining.

Method of making a packaged semiconductor die including heat sink with

Packaged semiconductor die including heat sink with locking feature

A ball grid array package and low cost method for manufacture of the same is disclosed herein. The ball grid array package includes a thermal conductor which is a linearly co-extensive outer layer of an interconnection substrate and forms the outer surface of the ball grid array package. An integrated circuit chip is positioned on the underside of the package in a well region. The well region is either formed directly in the interconnection substrate or is formed by the application of a dam. The well region is then filled with an insulating encapsulant material to a predetermined level.

Ball grid array integrated circuit package with thermal conductor

An inexpensive packaged integrated circuit with improved heat dissipative capacity and electrical performance. In one embodiment, the packaged integrated circuit includes a semiconductor die, a plurality of electrically conductive package leads, a thermal induction plate and a plurality of electrically conductive bond wires. A surface of the thermal induction plate may remain exposed outside the package. The thermal induction plate reduces package lead inductance and provides shielding of electromagnetic radiation that can cause electromagnetic interference. Preferably, holes are formed through the thermal induction plate to enhance flow of the package material during formation of a package and provide interlocking of the package to the remainder of the integrated circuit. In another embodiment, the packaged integrated circuit further includes a heat sink having a surface exposed to the exterior of the package. The heat sink may also perform an electrical function such as, for instance, acting as a power or ground plane. One or more generally conductive layers can be added to either of the above embodiments. The generally conductive layer or layers may be used to provide ground planes, power planes and/or electrically conductive traces for signal routing or an interconnect ring. The generally conductive layer or layers enable uniform power and ground supplies to be provided to the circuitry formed on the die, reduce package lead inductance, provide decoupling capacitances that reduce switching noise and crosstalk, and allow increased flexibility in the placement of particular circuit components.

Semiconductor device having a thermal dissipator and electromagnetic

An integrated circuit package, and a method for forming the integrated circuit package, including a single layer or multilayer substrate in which interconnection vias are formed is described. Laser energy is swept across a surface of a mask in which holes have been formed. Laser energy passing through the holes of the mask forms vias in a substrate held in place below the mask. The laser energy is swept at such a speed and is maintained at such an energy level that the laser energy forms vias in the substrate, but does not penetrate a set of leads attached to the substrate. Vias may be formed in this way by either a mask imaging, contact mask or conformal mask technique. The laser energy is emitted from a non-thermal (e.g., excimer) laser. The substrate is formed of an organic (e.g., epoxy) resin. The resin may include reinforcing fibers (e.g., aramid fibers). Substrates may be formed on one or both sides of the set of leads. After formation in the substrate, the vias are coated with an electrically conductive material. The method of via formation is fast, inexpensive, achieves higher via density, and avoids overheating of the substrate.

Integrated circuit package with via interconnections formed in a

Method for forming a semiconductor device having a thermal dissipator

According to the invention, a method and structure for flip chip interconnection of an integrated circuit chip to a substrate is provided. The method and structure of the invention overcome the problems associated with interconnecting the chip to the substrate by wirebonding and are less expensive than prior art flip chip interconnection methods and structures. Conventional integrated circuit chips that have been made using wafer fabrication processes for wirebonding chip-level interconnection are electrically connected to a substrate using a flip chip interconnection. Conventional wirebonding equipment can be used to bump chips for use in the invention. In one embodiment of the invention, an integrated circuit includes a semiconductor die mounted on a substrate such that electrically conductive material formed on each of the bond pads of the semiconductor die extends through a corresponding well formed in a dielectric layer on the substrate to contact electrically conductive material formed in the surface of the substrate on which the dielectric layer is situated. In another embodiment of the invention, the electrically conductive material is a coined ball bond, which can have, for instance, a conical section on top of a base section. The wells can be formed by any of a number of methods such as mechanical drilling, laser drilling, chemical etching or plasma etching.

Method for interconnection of integrated circuit chip and substrate

An integrated circuit package including a heat sink is disclosed. The package incorporates an sealing (or locking) ring located circumferentially around the heat sink to provide a better seal between the encapsulant and heat sink and to reduce the possibility that contaminants from outside the package will reach the interior semiconductor die. A stress relief section is formed in the package leads and a dielectric adhesive material is used to attach the package leads to a heat sink surface. The dielectric adhesive creates a secure bond between leads and heat sink, allows heat transfer from the leads to the heat sink, and prevents shorting of the leads to the heat sink.

Plastic molded package with heat sink for integrated circuit devices

Method for forming an integrated circuit package with via interconnection

A ball grid array is formed by mounting and electrically connecting one or more electronic devices to a substrate in which vias are formed to interconnect electrically conductive traces formed in a surface of the substrate to solder ball pads formed at an opposite surface of the substrate. The vias are formed by mechanical or laser drilling. Solder balls are formed on each of the pads and are reflow-attached to, for instance, a printed circuit board. The electronic components can include one or more integrated circuit chips, as well as passive components. The electronic components are attached to the substrate using wirebonding, TAB or flip chip connection. An encapsulating material is applied to encapsulate the electronic devices.

Ball grid array with via interconnection

An improved integrated circuit package including a heat sink and an improved method for making the package is disclosed. The package incorporates an improved sealing (or locking) ring located circumferentially around the heat sink to provide a better seal between the encapsulant and heat sink and to reduce the possibility that contaminants from outside the package will reach the interior semiconductor die. A stress relief section is formed in the package leads and a dielectric adhesive material is used to attach the package leads to a heat sink surface. The dielectric adhesive creates a secure bond between leads and heat sink, allows heat transfer from the leads to the heat sink, and prevents shorting of the leads to the heat sink. An improved method for making the package involves creating a dimensional mismatch between the thickness of the heat sink and a corresponding dimension of the mold cavity so as to provide a tighter seal between a heat sink surface that will be exposed to the exterior of the finished package and the mold cavity during the encapsulation process to prevent encapsulant from forming on the exposed heat sink surface. Stresses in the leadframe created during encapsulation are mitigated by the stress relief section in the leads.

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Scottsdale, AZ, United States of America

Robert C Marrs