Qorvo Us, Inc.

Triquint Semiconductor Corporation

Robert C Hartmann

Thomas Scott Morris

Frank J Juskey

Howard Terry Glascock

Charles E Carpenter

Jose F Ordonez

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.

Substrate structure with selective surface finishes for flip chip assembly

The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area.

Semiconductor package having a substrate structure with selective surface finishes

The present disclosure relates to a packaging process using a low pressure encapsulant. According to an exemplary process, an assembly including a substrate, a surface mounted device (SMD) mounted on the substrate, and a space between the SMD and the substrate is provided. The SMD has a sealed cavity biased towards the substrate. A sheet mold compound is laid over the SMD and the assembly is heated such that the sheet mold compound transitions to a liquid phase to form a molten mold compound. Next, the assembly is subjected to a vacuum that creates a negative atmosphere allowing the molten mold compound to flow towards the top surface of the substrate and about the SMD. The molten mold compound is then pressed towards the substrate at a low pressure (&#x3c;=2 Mpa) such that the space between the SMD and the substrate is substantially filled and the SMD is substantially encapsulated.

Low pressure encapsulant for size-reduced semiconductor package

Embodiments include but are not limited to apparatuses and systems including microelectronic devices including a package substrate, a plurality of electronic components disposed on and electrically coupled with the package substrate at one or more sides of the package substrate, one or more hollow cavity sheet molds surrounding the plurality of electronic components and coupled with one or more sides of the package substrate, and a plurality of through-mold vias to couple the package substrate with an external surface of at least one of the one or more hollow cavity sheet molds. The microelectronic device may be a chip-scale package or module. Methods and systems for making the same also are described.

Ultrathin flip-chip packaging techniques and configurations

A wafer level package includes an epoxy layer formed on an adhesive covered substrate during manufacturing for securing electrical components in place prior to being embedded in a molded material. An electrically conductive block is fixed in the epoxy layer. Vias are formed for accessing face up component contacts using a metalized layer on the surface of the molded material. After stripping the adhesive and substrate, the epoxy layer is penetrated to expose electrical contacts for face down components. An electrical connection is made between the face up and face down components using the block. Optionally, a dielectric layer covers the molded material and a second metalized layer placed on the dielectric layer to carry another electrical component embedded in a second dielectric layer covering the first dielectric layer. Thus a stacked component arrangement including multiple die and passive components is effectively fabricated into the wafer level package.

Growing community of inventors

Opopka, FL, United States of America

Robert C Hartmann