Adeia Semiconductor Bonding Technologies Inc.

Tessera Technologies Ireland Limited

Robert Burtzlaff

Giles Humpston

Belgacem Haba

David Bazeley Tuckerman

Vage Oganesian

Craig S Mitchell

David Ovrutsky

Michael James Nystrom

Michael Warner

Andrey Grinman

Charles Rosenstein

Osher Avsian

Felix Hazanovich

Yulia Aksenton

Avi Dayan

Ilya Hecht

Mitchell Hayes Reifel

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Wafer level chip packaging

A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

Back-face and edge interconnects for lidded package

Growing community of inventors

San Jose, CA, United States of America

Robert Burtzlaff