Advanced Micro Devices Corporation

Spansion Llc.

Robert Bertram Ogle, Jr

Derick J Wristers

Arvind Halliyal

Ming-Yin Hao

Mark W Randolph

Chi K Chang

Effiong Etukudo Ibok

Joong Jeon

Lei Xue

Meng Ding

Fred Cheung

A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Memory cell system using silicon-rich nitride

A process to deposit a silicon dioxide layer on a silicon nitride layer for an ONO stack of a floating gate transistor. Silicon dioxide is deposited on a silicon nitride layer and annealed in a batch furnace or a single wafer rapid thermal anneal tool in a nitrogen oxide (NO) or nitrous oxide (N O) ambient environment.

Process for treating ONO dielectric film of a floating gate memory cell

A process for fabricating a semiconductor device, including providing a semiconductor substrate; depositing on the semiconductor substrate a layer of a high-K gate dielectric material; depositing on the gate dielectric material layer a polysilicon or polysilicon-germanium gate electrode layer, in which the step of depositing the polysilicon or polysilicon-germanium gate electrode layer includes providing non-reducing conditions in a CVD apparatus.

Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material

A process for growing an ultra-thin dielelctric layer for use as a MOSFET gate or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density electron traps, and impedes dopant impurity diffusion from/to the dielelctric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Process for reliable ultrathin oxynitride formation

A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

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San Jose, CA, United States of America

Robert Bertram Ogle, Jr