Intel Corporation

Other

Tahoe Research, Ltd.

Robert Alan May

Kristof Darmawikarta

Sri Ranga Sai Boyapati

Srinivas V Pietambaram

Hiroki Tanaka

Aleksandar Aleksov

Amruthavalli Pallavi Alur

Robert L Sankman

Islam A Salama

Steve S Cho

Rahul N Manepalli

Sheng C Li

Chung Kwang Christopher Tan

Javier Soto Gonzalez

Wei-Lun Kane Jen

Andrew James Brown

Jason M Gamba

Jung Kyu Han

Thomas Heaton

Ali Lehaf

Leonel R Arana

Rahul Jain

Tarek A Ibrahim

Changhua Liu

Bai Nie

Sameer Paital

Jesse Jones

Frank Truong

Xiaoying Guo

Oscar Ojeda

Daniel N Sobieski

Xiaoqian Li

Sri Ranga Sai Sai Boyapati

Adel A Elsherbini

Sanka Ganesan

Ram S Viswanath

Gang Duan

Xavier Francois Brun

Manish Dubey

Lauren Ashley Link

Chung Kwang Tan

Kyu Oh Lee

Dilan Seneviratne

Yikang Deng

Jeremy D Ecton

Sai Vadlamani

Prithwish Chatterjee

Praneeth Kumar Akkinepally

Lilia May

Jonathan Rosch

Kwangmo Lim

Telesphor Kamgaing

Brandon C Marin

Siddharth K Alur

Amanda E Schuckman

Sashi S Kandanur

Arnab Roy

Ravindranadh T Eluri

Kwangmo Chris Lim

Vahidreza Parichehreh

Kristof Darmawaikarta

Maroun D Moussallem

Omkar G Karhade

Nitin A Deshpande

Chong Zhang

Suddhasattwa Nad

Sri Chaitra Jyotsna Chavali

Ji Yong Park

Bharat P Penmecha

Sri Chaitra J Chavali

Yosuke Kanaoka

Whitney Michael Bryks

Srinivas Venkata Ramanuja Pietambaram

Arnab Sarkar

Divya Pratap

Sandeep Gaan

Eddie Gamble, Jr

Brian Bueza

Chi-Mon Chen

Lisa Ying Ying Chen

Robin Shea McRee

Omkar Karhade

Nitin Deshpande

Kristof Darmawkarta

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

First layer interconnect first on carrier approach for EMIB patch

Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

Lithographic cavity formation to enable EMIB bump pitch scaling

A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

Die interconnect substrate, an electrical device and a method for forming a die interconnect substrate

An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and the magnetic material is to rotate a polarization vector of light incoming to the optical interconnect. An optical fiber interface port is immediately adjacent to the first lens. The second lens is immediately adjacent to an optical interface of the optical die.

Magneto-optical Kerr effect interconnects for photonic packaging

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

Multi-chip package with high density interconnects

A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers

Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.

Integrated circuit package supports

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

Microelectronic component having molded regions with through-mold vias

Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

EMIB patch on glass laminate substrate

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Microelectronic device with embedded die substrate on interposer

A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Device and method of very high density routing used with embedded multi-die interconnect bridge

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

Subtractive etch resolution implementing a functional thin metal resist

Growing community of inventors

Chandler, AZ, United States of America

Robert Alan May