Advanced Micro Devices Corporation

Spansion Llc.

Intermolecular, Inc.

Other

Advanced Micro Devices, Inc. and Spansion LLC

Robert A Huertas

Minh Van Ngo

Lu You

Hieu T Pham

Dawn M Hopper

Angela Tai Hui

Christy Mei-Chu Woo

Ning Cheng

Alexander H Nickel

Minh Quoc Tran

Hirokazu Tokuno

Pei-Yuan Gao

Erik Wilson

Tazrien Kamal

Hartmut Ruelke

Tyagamohan Gottipati

Yun Yu Wang

Paul Raymond Besser

Mark T Ramsbey

Jeffrey Allan Shields

Arvind Halliyal

Jaeyong Park

Randall Higuchi

Jeff P Erhardt

Ercan Adem

King Wai Kelwin Ko

Clarence B Ferguson

Daniel V Rowland

Tony P Chiang

Imran Hashim

Richard J Huang

Suzette Keefe Pangrle

Simon S Chan

Joerg Hohage

Federico Nardi

Vidyut Gopal

Wenmei Li

Jean Yee-Mei Yang

Inkuk Kang

Minh-Van Ngo

Christine Hau-Riege

Ryan C Clarke

Terri Jo Kitson

Amir Hossein Jafarpour

Steve Avanzino

Lothar Mergili

Jeyong Park

Norein (Narendra) Patel

Norein Narendra Patel

Forming a resistive switching layer having a vertical interface can generate defects confined along the interface between two electrodes. The confined defects can form a pre-determined region for filament formation and dissolution, leading to low power resistive switching and low program voltage or current variability. In addition, the filament forming process of the resistive memory device can be omitted due to the existence of the confined defects.

Vertical oxide-oxide interface for forming-free, low power and low variability RRAM devices

A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments.

Interfacial oxide used as switching layer in a nonvolatile resistive memory element

During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 &#x212b; to about 500 &#x212b;, curing after deposition, as by UV radiation or by heating at a temperature of about 400&#xb0; C. to about 1000&#xb0; C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

Gap-filling with uniform properties

Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an Natmosphere containing low Hor no H, and at temperatures less than 200&#xb0; C., e.g., 100&#xb0; C. to 150&#xb0; C.

Cu annealing for improved data retention in flash memory devices

Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si&#x2014;H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si&#x2014;H bonds on the first silicon nitride layer for reduced charge loss.

Semiconductor devices with copper interconnects and composite silicon nitride capping layers

A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.

Interlayer dielectric for charge loss improvement

Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 &#x212b; to 600 &#x212b;, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

Undoped oxide liner/BPSG for improved data retention

A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing

An exposed surface of inlaid Cu is plasma treated for improved capping layer adhesion while controlling plasma conditions to avoid damaging porous low-k materials. Embodiments include forming a dual damascene opening in a porous dielectric material having a dielectric constant (k) of up to 2.4, e.g., 2.0 to 2.2, filling the opening with Cu, conducting CMP, plasma treating the exposed Cu surface in NHor Hat a low power, e.g., 75 to 125 watts, for a short period of time, e.g., 2 to 8 seconds, without etching the porous low-k material and depositing a capping layer, e.g., silicon nitride or silicon carbide.

Method of treating inlaid copper for improved capping layer adhesion without damaging porous low-k materials

The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH and N , ramping up the introduction of trimethylsilane and then initiating deposition of a silicon carbide capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH plasma diluted with N , shutting off the power, discontinuing the N flow and introducing He, then ramping up the introduction of trimethylsilane in three stages, and then initiating plasma enhanced chemical vapor deposition of a silicon carbide capping layer, while maintaining substantially the same temperature of 335&deg; C. throughout plasma treatment and silicon carbide capping layer deposition. Embodiments also include forming Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than 3.9.

Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance

A silicon oxide layer is deposited at a thickness of about 50 &angst; or less by a multi-stage method comprising depositing a sub-layer of silicon oxide in each stage by PECVD at a low deposition rate. Embodiments include depositing a silicon dioxide liner over a gate electrode in at least four stages, each stage comprising depositing a sub-layer at a thickness of 10 &angst; or less.

Multi-stage, low deposition rate PECVD oxide

A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL

A thin silicon nitride layer is deposited at an ultra low deposition rate by PECVD by reducing the NH flow rate and/or reducing the SiH flow rate. Embodiments include depositing a thin layer of silicon nitride, e.g., 100 &angst; or less, on a thin silicon oxide liner over a gate electrode, at an NH flow rate of 100 to 800 sccm, a SiH flow rate of 50 to 100 sccm and a reduced pressure of 0.8 to 1.8 Torr. Embodiments of the present invention further include depositing the silicon nitride layer in multiple deposition stages, e.g., depositing the silicon nitride layer in five deposition stages of 20 &angst; each.

Ultra low deposition rate PECVD silicon nitride

Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Nitrogen-plasma treatment for reduced nickel silicide bridging

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Hollister, CA, United States of America

Robert A Huertas