International Rectifier Corporation

Efficient Power Conversion Corporation

California Institute of Technology

Infineon Technologies Americas Corp.

United States of America As Represented by the Administrator of Nasa

Robert A Beach

Jianjun Cao

Paul Bridger

Alexander Lidow

Alana Nakata

Guangyuan Zhao

Robert Strittmatter

Seshadri Kolluri

Yanping Ma

Chunhua Zhou

Guang Yuan Zhao

Ming-Kun Chiang

Jiali Cao

Zhi He

Fang Chang Liu

Agus Jauhar

Michael A Briere

Robert P Strittmatter

Daniel Marvin Kinzer

Michael Andrew De Rooij

Johan Tjeerd Strydom

Thomas C McGill

Fang-Chang Liu

Thomas Herman

Michael A De Rooji

Shouleh Nikzad

Ravi Ananth

Edward Lee

Michael Chapman

Stephen L Colino

Paul M Bridger

Yoganand Saripalli

Zhikai Tang

Mike Briere

Lloyd Douglas Bell

Guang Yuang Zhao

A cascaded bootstrapping gate driver configured to provide quick turn-on of a high side power FET and low static current consumption. The cascaded bootstrapping gate driver includes an initial bootstrapping stage with a resistor to decrease static current consumption during transistor turn-off. A secondary bootstrapping stage is driven by the initial bootstrapping stage and includes a GaN FET transistor with a low on resistance in place of the resistor. The source terminal of the GaN FET transistor provides a gate driving voltage to the high side power switch FET. The low on-resistance of the GaN FET transistor provides quick turn-on of the high side power FET. Transistors in the cascaded bootstrapping gate driver are preferably enhancement mode GaN FETs and may be integrated into a single semiconductor die.

Cascaded bootstrapping GaN power switch and driver

An enhancement-mode transistor gate structure which includes a spacer layer of GaN disposed above a barrier layer, a first layer of pGaN above the spacer layer, an etch stop layer of p-type Al-containing column III-V material, for example, pAlGaN or pAlInGaN, disposed above the first p-GaN layer, and a second p-GaN layer, having a greater thickness than the first p-GaN layer, disposed over the etch stop layer. The etch stop layer minimizes damage to the underlying barrier layer during gate etching steps, and improves GaN spacer thickness uniformity.

Enhancement-mode GaN transistor with selective and nonselective etch layers for improved uniformity in GaN spacer thickness

Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Semiconductor devices with back surface isolation

A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

GaN transistors with polysilicon layers used for creating additional components

A gallium nitride (GaN) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the gate and drain (near the gate) minimizes the gate leakage and fields near the gate that cause high gate-drain charge (Q). A second insulator (or multiple insulators), disposed between the first insulator and the drain, minimizes electric fields at the drain contact and provides a high density of charge in the channel for low on-resistance.

Multi-step surface passivation structures and methods for fabricating same

A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.

Flip chip interconnection with reduced current density

A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps.

Fabrication of semiconductor device using alternating high and low temperature layers

A III-nitride power semiconductor device that includes a field relaxation feature to relax the electric fields around the gate thereof to improve the breakdown voltage of the device.

III-nitride power semiconductor with a field relaxation feature

An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.

Integrated circuit with matching threshold voltages and method for making same

A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.

High performance III-nitride power device

A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.

GaN device with reduced output capacitance and process for making same

A GaN transistor with polysilicon layers for creating additional components for an integrated circuit. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

GaN transistors with polysilicon layers for creating additional components

Growing community of inventors

Pasadena, CA, United States of America

Robert A Beach