Imec

Imec Vzw

Interuniversitair Microelektronica Centrum (imec)

Katholieke Universiteit Leuven, Ku Leuven R&d

Stmicroelectronics (crolles 2) Sas

Katholieke Universiteit Leuven

Rita Rooyackers

Anne S Verhulst

Nadine Collaert

Ricardo Alves Donaton

Mikhail Rodionovich Baklanov

Marc Marcel Heyns

Geert Eneman

Malgorzata Jurczak

Ludo Deferm

Goncal Badenes

Daniele Leonelli

Philippe Jansen

Rita Verbeeck

Karen Irma Maex

Axel Nackaerts

Serge Vanhaelemeersch

Liesbeth Witters

Roger Loo

Wim Dehaene

Naoto Horiguchi

Cedric Huyghebaert

Damien Lenoble

Anabela Veloso

Amey Mahadev Walke

Geoffrey Pourtois

Stefan De Gendt

Min-Soo Kim

Denis Shamiryan

Peter Verheyen

Anne Vandooren

Frederik Leys

Quentin Smets

Kirklen Henson

Karen Irma Josef Maex

Emmanuel Augendre

A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.

Monolithic integration of semiconductor materials

An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Method for forming a transistor structure comprising a fin-shaped channel structure

A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.

Heterosection tunnel field-effect transistor (TFET)

A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Method for manufacturing transistor and associated device

A Tunnel Field Effect Transistor device (TFET) made of at least following layers: a highly doped drain layer, a highly doped source layer, a channel layer, a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer, and a highly doped pocket layer extending in between and along the gate dielectric layer and the source layer, characterized in that the pocket layer extends to between and along the source layer and the channel layer.

Tunnel field effect transistor device and method for making the device

A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.

Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor

The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device

A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin comprising a top surface, at least one sidewall surface, and at least one corner. A supersaturation of point defects is created in the at least one fin. The at least one fin is annealed and then cooled down such that semiconductor atoms of the semiconductor material migrate via the point defects.

Method for fabricating a semiconductor device and the semiconductor device made thereof

One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method includes providing a substrate having a first and a second substrate area, the first area including at least one gate stack. The method includes applying a poly-Si or poly-SiGe top layer on the substrate, the top layer being etchable with the same etch chemistry as the substrate. The method includes removing the poly-Si or poly-SiGe top layer from the first area selectively towards the poly-Si or poly-SiGe top layer in the second area. The method includes removing simultaneously the poly-Si or poly-SiGe top layer on the second area and at least a part of the substrate in the S/D areas of the first area selectively to the gate stack. The method includes performing a selective epitaxial growth of S/D areas in the first area.

Method for selective epitaxial growth of source/drain areas

A method for forming at least one quantum dot at at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (w) and having a local width variation at at least one predetermined location where the at least one quantum dot has to be formed. The local width variation has an amplitude (A) of between about 20 nm and 35 nm higher than the width wof the at least one line. The at least one line is patterned to form at least one quantum dot. A design for a lithographic mask for use with the method and a method for making such a design are also disclosed.

Method for making quantum dots

A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a diffusion barrier layer on the first region, performing a hydrogen anneal such that the strain in the second region is relaxed.

Method of fabricating a strained multi-gate transistor

The present invention is related to a method for producing semiconductor devices from a semiconductor substrate, comprising providing a substrate having on its surface a number of elevated areas separated by areas which are at a lower level. Each elevated area has at its top surface a first layer of a material which is resistant to Chemical Mechanical Polishing (CMP). The method further comprises depositing a layer of a dielectric on top of the whole of said substrate, thereby filling the gaps between said elevated areas. The method further comprises depositing a second layer of a material which is resistant to CMP on top of the whole of said substrate. The method further comprises removing parts of the second CMP resistant layer and of dielectric layer. The method further comprises performing a CMP step and terminating the CMP step at the location of said first and second CMP resistant layers.

Method of producing semiconductor devices using chemical mechanical polishing

A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.

Semiconductor device with selectable gate thickness and method of manufacturing such devices

A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.

MIS transistors with a metal gate and high-k dielectric and method of forming

The present invention relates to methods for controlling the etching rate of CoSi,layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schotky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.

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Kessel-lo, Belgium

Rita Rooyackers