International Business Machines Corporation

Micron Technology Incorporated

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Rishikesh Krishnan

Michael Patrick Chudzik

Judson Robert Holt

Noel Rocklein

Yue Ke

Siddarth A Krishnan

Vishwanath Bhat

Eric C Harley

Takashi Ando

Henry K Utomo

Herbert Lei Ho

Unoh Kwon

Joseph Francis Shepard, Jr

Nicolas L Breil

Keith Howard Tabakman

John A Smythe

Chris M Carlson

Bhaskar Srinivasan

Shahab Siddiqui

Oh-Jung Kwon

Daniel James Dechene

Kai Zhao

Charlotte DeWan Adams

Vidya Srividya

Kern Rim

Dan Gealy

Ricardo Alves Donaton

Daniel Gealy

Donghun Kang

Dong Hun Kang

Jeff Hull

Alexander Reznicek

Ruilong Xie

Vijay Narayanan

Keith Kwong Hon Wong

Martin Michael Frank

Eduard Albert Cartier

Koji Watanabe

Barry P Linder

Paul Christian Parries

Yiheng Xu

Hongwen Yan

Claude Ortolland

Min Dai

Bharat V Krishnan

Aritra Dasgupta

Bachir Dirahoui

David F Hilscher

Kangguo Cheng

Junli Wang

Hui Zang

Oleg Gluschenkov

Dechao Guo

Balasubramanian Pranatharthiharan

Julien Frougier

Ruqiang Bao

Christian Lavoie

Dominic Joseph Schepis

Brian Joseph Greene

Kisik Choi

Renee Tong Mo

F Daniel Gealy

Rajasekhar Venigalla

Stuart A Sieg

Byeong Yeol Kim

Karen A Nummy

Sunfei Fang

Timothy James McArdle

Somnath Ghosh

Daewon Yang

Tek Po Rinus Lee

Qun Gao

Rinus Tek Po Lee

Eric C T Harley

Dong-Ick Lee

Annie Levesque

Fuad H Al-Amoody

Yinxiao Yang

Edward R Engbrecht

Joseph K Kassim

Youngjin Choi

Jeff Hall

Curtis Durfee

A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

Stacked FETS with non-shared work function metals

Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance

Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

Buried power rails located in a base layer including first, second, and third etch stop layers

A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

Gate oxide for nanosheet transistor devices

A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

Device with highly active acceptor doping and method of production thereof

The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.

Fin structures

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500&#xb0; C., so as to increase the density of the cured insulator.

Microwave annealing of flowable oxides with trap layers

A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

Trench metal insulator metal capacitor with oxygen gettering layer

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Hydroxyl group termination for nucleation of a dielectric metallic oxide

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Poughkeepsie, NY, United States of America

Rishikesh Krishnan