Spansion Llc.

Cypress Semiconductor Corporation

Fasl LLC

Advanced Micro Devices Corporation

Other

Globalfoundries Inc.

Infineon Technologies LLC

Rinji Sugino

Hidehiko Shiraiwa

Minh Van Ngo

Arvind Halliyal

Tazrien Kamal

Lei Xue

Jean Y Yang

Shenqing Fang

Kuo-Tung Chang

Mark T Ramsbey

Ching-Huang Lu

Kenichi Ohtsuka

Youseok Suh

Simon Siu-Sing Chan

Jaeyong Park

Fred T K Cheung

Yi Ma

Dawn M Hopper

Takashi Whitney Orimoto

Yider Wu

Robert B Ogle

Joong Jeon

Meng Ding

Jean Yee-Mei Yang

Inkuk Kang

Pei-Yuan Gao

Jeffrey Sinclair Glick

Fei Wang

Krishnaswamy Ramkumar

Angela Tai Hui

Scott Allan Bell

Zhigang Wang

Chi K Chang

Hiroyuki Kinoshita

Simon S Chan

Timothy J Thurgate

Ning Cheng

Chun Chen

Kuo Tung Chang

Amol Ramesh Joshi

Chungho Lee

Yukio Hayakawa

Huaqiang Wu

Harpreet Kaur Sachar

Hirokazu Tokuno

Jayendra D Bhakta

Cinti Xiaohua Chen

Hiroyuki Nansei

Michael Brennan

Kazuhiro Mizutani

Gang Xue

Eunha Kim

Yun Wu

Pavel Fastenko

Amir Hossein Jafarpour

Bradley Marc Davis

Takayuki Maruyama

Hajime Wada

Shenging Fang

Jeremy Wahl

Renhua Zhang

A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.

Inter-layer insulator for electronic devices and apparatus for forming same

An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Self-aligned trench isolation in integrated circuits

A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.

Memory device with multi-layer channel and charge trapping layer

A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections.

Distribution of gas over a semiconductor wafer in batch processing

A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.

Buried trench isolation in integrated circuits

A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate.

Formation of gate sidewall structure

Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.

Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges

A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Memory cell system with multiple nitride layers

A method for semiconductor device fabrication is provided. The present invention is directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. At least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.

Patterned dummy wafers loading in batch type CVD

A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

Method for forming a semiconductor layer with improved gap filling properties

Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

Gate replacement with top oxide regrowth for the top oxide improvement

A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.

Memory device protection layer

A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.

Memory cell system with charge trap

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San Jose, CA, United States of America

Rinji Sugino