Kabushiki Kaisha Toshiba

Winbond Electronics Corporation

Other

Powerchip Technology Corporation

Toshiba Memory Corporation

Phison Electronics Corporation

Powerflash Technology Corporation

Powerchip Corporation

Kioxia Corporation

Toshiba Microelectronics Corporation

Im Solution Co., Ltd.

Robustflash Technologies Ltd.

Riichiro Shirota

Fumitaka Arai

Seiichi Aritome

Tomoharu Tanaka

Yuji Takeuchi

Masaki Momodomi

Masayuki Ichige

Takashi Mori

Kikuko Sugimae

Yoshiyuki Tanaka

Ryouhei Kirisawa

Yoshihisa Iwata

Tetsuo Endoh

Yasuo Itoh

Michiharu Matsui

Seiichi Mori

Masamichi Asano

Fujio Masuoka

Takeshi Kamigaichi

Hideko Odaira

Hirohisa Iizuka

Ken Takeuchi

Hideo Kato

Yutaka Okamoto

Hiroto Nakai

Kaoru Tokushige

Susumu Fujimura

Hiroshi Watanabe

Yoshio Ozawa

Kazuhiro Shimizu

Akihito Yamamoto

Hiroaki Hazama

Yasuhiko Matsunaga

Akira Shimizu

Ryozo Nakayama

Toru Tanzawa

Toshitake Yaegashi

Atsuhiro Sato

Akira Goda

Kazunori Ohuchi

Shinji Satoh

Masahiro Kiyotoshi

Makoto Sakuma

Te-Chang Tseng

Naoki Koido

Koji Sakui

Nobutoshi Aoki

Susumu Shuto

Gertjan Hemink

Toshiyuki Enda

Hiroyoshi Tanimoto

Satoshi Inoue

Naoki Kusunoki

Yukihiro Nagai

Hiroshi Iwahashi

Ichiro Mizushima

Makoto Mizukami

Norihisa Arai

Shigeyoshi Watanabe

Kazuya Matsuzawa

Tohru Maruyama

Wakako Moriyama

Koji Hashimoto

Masaru Yano

Hiroyuki Kutsukake

Hideki Arakawa

Tatsuaki Kuji

Yoshihiko Saito

Masahiko Chiba

Ching-Hsiang Hsu

Wei Hung Lin

Hiroshi Nakamura

Cheng-Jye Liu

Takashi Miida

Tsai-Hao Kuo

Shinichiro Takatani

Hideaki Aochi

Masaru Kito

Ryota Katsumata

Masaru Kidoh

Takuya Futatsuyama

Atsuhiro Kinoshita

Osamu Ikeda

Kenichi Murooka

Kiyotaka Miyano

Akihiro Nitayama

Tadashi Iguchi

Masaki Kondo

Hiroaki Tsunoda

Makoto Senoo

Kazuhito Narita

Junji Koga

Hisataka Meguro

Takamitsu Ishihara

Naohiro Matsukawa

Eiji Kamiya

Katsutoshi Suito

Sanae Ito

Hitoshi Araki

An AND-type flash memory capable of achieving high integration after providing a miniaturized memory cell size includes: a plurality of diffusion regions () formed in a substrate in a column direction, a plurality of gates () formed between the opposite diffusion regions (), a selection control line (SGD), a selection control line (SGS), and a plurality of word lines (WLto WLn-). The selection control line (SGD) is connected to each gate of a bit line side selection transistor. The selection control line (SGS) is connected to each gate of a source line side selection transistor. The word lines (WLto WLn-) are connected to gates of memory cells. Each of the bit line side selection transistor, the source line side selection transistor, and the plurality of memory cells has a channel area in the row direction.

Flash memory with high integration

A NAND flash memory and manufacturing method thereof are provided. The NAND flash memory is capable of preventing a short circuit between gates extending along a vertical direction. The NAND flash memory includes a substrate; a plurality of channel stacks formed on the substrate and extending along an X direction; an interlayer dielectric formed between the channel stacks; a plurality of trenches formed apart from each other in the interlayer dielectric and arranged along a Y direction; an insulator stack including a charge storage layer formed to cover sidewalls of each of the trenches; and a plurality of conductive vertical gates elongating along the vertical direction in a space formed by the insulator stack in each of the trenches and extending along the Y direction.

NAND flash memory and manufacturing method thereof

A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a groupof word lines WLto WLi−1, a groupof word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk−1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread, Vread, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.

Semiconductor memory device and reading method

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Semiconductor memory and method of manufacturing the same

A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.

NAND flash memory with reduced planar size

A normally-off vertical nitride semiconductor transistor device with low threshold voltage variation includes a drift layer containing a nitride semiconductor, a channel region electrically connected to the drift layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The gate insulating film includes at least a first insulating film located at the channel region side, a second insulating film located at the gate electrode side, and a third insulating film between the second insulating film and the gate electrode, wherein the second insulating film has charge traps with energy levels located inside the band gaps of both the first and third insulating films, and the threshold voltage is adjusted by charges accumulated in the charge traps. The threshold voltage is used to block flowing current by substantially eliminating conduction carriers of the channel region by voltage applied to the gate electrode.

Vertical nitride semiconductor transistor device

An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memoryincludes a plurality of columnar portions, a plurality of charge accumulating portionsand a plurality of control gates. The columnar portionsextend from a surface of a silicon substratein a vertical direction and include an active region. The charge accumulating portionsare formed by way of surrounding a side portion of each columnar portion. The control gatesare formed by way of surrounding a side portion of each charge accumulating portion. One end portion of the columnar portionis electrically connected to a bit linevia a contact hole, and another end portion of the columnar portionis electrically connected to a conductive region formed on a surface of the silicon substrate

NOR flash memory and manufacturing method thereof

A nitride semiconductor transistor device is disclosed. The device includes a first nitride semiconductor layer disposed over a substrate, and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor disposed over the first nitride semiconductor layer. Over the second nitride semiconductor layer, a first insulating film, a charge-storing gate electrode, a second insulating film, and a second gate electrode are formed in order thereon. A source electrode and a drain electrode are disposed over the second nitride semiconductor layer interposing the charge-storing gate electrode in a plane direction. The device further includes a first gate electrode capacitively coupling with the charge-storing gate electrode with an insulating film therebetween forming a first capacitor, and the charge-storing gate electrode is charged by an electron injection from the first gate electrode through the first capacitor.

Normally-off nitride semiconductor transistor device

A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.

Power semiconductor device

NOR flash memory that includes three-dimensional memory cells is provided. In the NOR flash memory of the present disclosure, one memory cell includes one memory transistor and one selection transistor. A common sourceis formed over a silicon substrate, and an active regionextending in a vertical direction to electrically connect to the common sourceis formed. A control gateof the memory transistor and a selection gate lineof the selection transistor are formed to surround a side portion of the active region, and a top portion of the active regionis electrically connected to a bit line

NOR flash memory and method of fabricating the same

A network includes a logical network and a physical network. The logical network includes a plurality of logical nodes. Each logical node is connected to a respective identification core. Each identification core includes at least one semiconductor chip having a physical randomness. Each semiconductor chip generates one of a plurality of pairs of private keys and public keys based on the physical randomness thereof according to an input received by the one of the at least one semiconductor chip under a public key cryptography. One of the public keys is regarded as a logical address of one of the logical nodes, which is connected to one of the identification cores. The physical network includes a plurality of physical nodes. Each identification core is one of components in each physical node. The logical network is uniquely linked to the physical network by the pairs of private keys and public keys.

Network without abuse of a private key

A semiconductor apparatus includes a semiconductor chip, with the semiconductor chip including a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses is randomly formed related to a part or an entirety of the modular area of the modular region. The distribution of the retrieved redundant addresses is irreversible, with a random number representing physical properties intrinsic to the semiconductor chip and providing copy protection. When another semiconductor chip uses the distribution of the retrieved redundant addresses the another semiconductor chip will malfunction. The test circuit outputs a random number generated from the distribution of the retrieved redundant addresses according to a specification code received from a physical-chip-identification measuring device.

Semiconductor apparatus with reduced risks of chip counterfeiting and network invasion

A network of electronic appliances includes a plurality of network units of electronic appliances. The network units include a first network unit and a plurality of second network units. The first network unit is connected to at least one of the second network units. Each of the network units includes a stem server and a plurality of peripheral devices connected to the stem server. The stem server includes at least one passcode and at least one list of a plurality of registration codes. Each list is associated to a respective passcode. Each registration code of one list associating to one passcode corresponds to a respective peripheral device. Each registration code is generated in response to a respective passcode using physical randomness of a respective peripheral device in correspondence to the passcode. An address of each identification cell is defined by several word lines and bit lines.

Electronic appliance and network of the same

Growing community of inventors

Fujisawa, Japan

Riichiro Shirota