United Test and Assembly Center Limited

Utac Headquarters Pte. Ltd.

Richard Te Gan

Nathapong Suthiwongsunthorn

Kian Teng Eng

Chuen Khiang Wang

Catherine Bee Liang Ng

Antonio Jr B Dimaano

Kriangsak Sae Le

Hien Boon Tan

Anthony Yi Sheng Sun

Roel Adeva Robles

Danny Retuta

Mary Annie Cheong

A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Semiconductor packages and methods of packaging semiconductor devices

A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.

Semiconductor package with under bump metallization aligned with open vias

Growing community of inventors

Singapore, Singapore

Richard Te Gan