Freescale Semiconductor,inc.

Motorola Corporation

Richard T Ida

Hongzhong Xu

James D Whitfield

Michael Baird

Sopan Joshi

Vijay Parthasarathy

William F Davis

Robert O Wagner

Daniel L Ziegler

Beth A Baumert

Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.

Process insensitive ESD protection device

Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Low voltage NMOS-based electrostatic discharge clamp

Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.

Electrostatic discharge protection device and method therefore

A low voltage thyristor is disclosed that can be used to provide protection during electrostatic discharge event. The thyristor is connected between voltage reference nodes having a common potential, such as ground nodes, that are isolated from one another during normal operating conditions. During an ESD event on one of the voltage reference nodes, the low voltage thyrister triggers, at a voltage of less than ten volts, to help discharge the ESD current through the otherwise isolated ground node.

Semiconductor apparatus

An overvoltage protection device (40) and a method for increasing the overvoltage current the device can carry. The overvoltage protection device (40) includes a Silicon Controlled Rectifier (SCR) (11) and an SCR enhance circuit (42). The SCR enhance circuit (42) provides the SCR (11) with an additional low resistance path to increase the amount of overvoltage shunt current the SCR (11) carries during an overvoltage event.

Overvoltage protection device and method for increasing shunt current

A protection circuit (20) protects a semiconductor device (10) from damage due to electrostatic charge transferred to a terminal (19) of the semiconductor device. A voltage follower (26) senses a voltage (V.sub.CHARGE) developed by the electrostatic charge to produce a follower voltage. A conduction path (30) is enabled with the follower voltage to discharge the electrostatic charge from the terminal before the voltage rises to a magnitude that damages the integrated circuit.

Semiconductor protection circuit and method

A method to extract at wafer probe the variation of lateral PNP basewidth of transistors formed in an integrated circuit which uses two lateral PNP devices having different and known basewidths before fabrication of the devices in the integrated circuit and then measuring the ratio of the saturation currents at wafer probe. The actual basewidth of the lateral PNP transistor is then related to the difference of the known basewidths of the two lateral PNP transistors and the ratio of the saturation measured currents thereof.

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Chandler, AZ, United States of America

Richard T Ida