International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Globalfoundries U.S. Inc.

Elpis Technologies Inc.

Richard Stephen Graf

Jeffrey P Gambino

Sudeep Mandal

David Justin West

Sebastian Theodore Ventrone

Robert K Leidy

David John Russell

Jeffrey C Maling

Jack Robert Smith

Ezra D B Hall

Charles H Wilson

Hanyi Ding

Wayne Harvey Woods, Jr

Nazmul Habib

Janak G Patel

Gary Ray Hill

Kibby B Horsford

Faraydon Pakbaz

Jay F Leonard

Manish Nayini

Sudipta Kumar Ray

Douglas Oliver Powell

Thomas Edward Lombardi

Vibhor Jain

Joseph Andrew Iadanza

Edward Crandal Cooney, Iii

Huahung Kao

Keishi Okamoto

Ivan L Wemple

Gary L Milo

Wai Ling Chung-Maloney

Sundeep Mandal

Luke England

Ronen Sinai

Haruo Itoh

An electronic device disposed in a package that includes: an interposer, fan-out interconnect (FOI), and a lid. The interposer having first size and first surface upon which die terminals (DTs) are disposed and are configured to electrically couple to integrated circuit die (IC), and second surface upon which substrate terminals (STs) are disposed and are configured to electrically couple to substrate. The IC has second size smaller than the first size, and the IC is mounted on the first surface in electrical contact with the DTs, the interposer is mounted on third surface, and the package substrate has third size, larger than the first size. The FOI establishes electrical interconnection between DTs and STs, the DTs have first pitch size and the STs have second pitch size, larger than first pitch size. The lid has first section, configured to abut fourth surface, and second section, mounted on the third surface.

Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure

A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.

Heat sink configuration for multi-chip module

An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

IC chip package with dummy solder structure under corner, and related method

An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

Enabling of functional logic in IC using thermal sequence enabling test

An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Dual bond pad structure for photonics

Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

Method of manufacturing chip-on-chip structure comprising sinterted pillars

Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.

Tamper detection for a chip package

Chip-on-chip structure and methods of manufacture

A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.

Producing wafer level packaging using leadframe strip and related device

The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.

Stacked dies using one or more interposers

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Low temperature fabrication of lateral thin film varistor

An IC chip package includes: a base substrate; an interposer substrate including a plurality of wires therein, the interposer substrate operatively coupled to the base substrate; and a processor operatively positioned on the interposer substrate. A memory is operatively positioned on the interposer substrate and operatively coupled to the processor through the interposer substrate. The memory includes: a 3D DRAM stack, a thermoelectric heat pump coupled directly to an uppermost layer of the 3D DRAM stack, and a memory controller operatively coupled to the 3D DRAM stack to control operation of the 3D DRAM stack. A temperature controller operatively coupled to the thermoelectric heat pump controls a temperature of the 3D DRAM stack using the thermoelectric heat pump. A lid may thermally couple to an uppermost surface of the processor and an uppermost surface of the thermoelectric heat pump.

Memory having thermoelectric heat pump and related IC chip package and method

Growing community of inventors

Gray, ME, United States of America

Richard Stephen Graf