Cadence Design Systems, Inc.

Richard Schoonover

Joseph Michael Swenton

Thomas Webster Bartenstein

David Sliwinski

Vivek Chickermane

Brion L Keller

Pradeep Nagaraj

SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.

Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test

Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times.

System to control insertion of care-bits in an IC test vector improved optical probing

Method and article of manufacture to generate IC test vector for synchronized physical probing

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Binghamton, NY, United States of America

Richard Schoonover