Advanced Micro Devices Corporation

Richard P Rouse

Ming Yin Hao

Effiong Etukudo Ibok

Judy Xilin An

Emi Ishida

Carl Robert Huster

Zoran Krivokapic

Donald L Wollesen

Zicheng Gary Ling

Che-Hoo Ng

Asim A Selcuk

Concetta E Riccobene

Ognjen Milic-Strkalj

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming source and drain regions that are recessed a prescribed depth below the main surface of the semiconductor substrate. Sidewall spacers and a silicide layer are subsequently formed on the gate electrode stack. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Method of making recessed source drains to reduce fringing capacitance

A semiconductor device with reduced leakage current is obtained by forming a non-uniform channel doping profile. A high impurity region of the opposite conductive type of a source region is formed between the channel region and source region by transient enhanced diffusion (TED). The high impurity region substantially reduces the threshold voltage rolling off problem.

Non-uniform channel profile via enhanced diffusion

Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.

Oxygen implantation for reduction of junction capacitance in MOS transistors

Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for &ldquo;latch up&rdquo; are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate insulator layer.

Indium retrograde channel doping for improved gate oxide reliability

CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type transistor shallow source/drain implants; forming relatively thin first sidewall spacers on the gates of both transistors; ion implanting a P-type impurity, e.g. BF,, to form shallow source/drain extension implants for the P-type transistor; forming relatively thick side wall spacers on the first sidewall spacers of both transistors; ion implanting, e.g. As, to form moderately or heavily doped N-type implants; activation annealing at a first temperature, e.g., about 1050&deg; C. to form the shallow N- and P-type source/drain extensions and moderately or heavily doped P-type source/drain regions; ion implanting a P-type impurity, e.g., BF,, to form moderately or heavily doped P-type source/drain implants; and activation annealing at a second temperature less than the first temperature, e.g., at about 1000&deg; C. to form moderately or heavily doped P type source/drain regions.

Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length

A method for manufacturing a field effect transistor (,) includes steps of forming a gate stack (,) on the surface (,) of a semiconductor substrate (,), and defining source/drain regions (,) on either side of the gate stack and a channel region (,) under the gate stack. The channel region has one end (,) proximate a first source/drain region and another end (,) proximate a second source/drain region. The method further includes forming a masking layer (,) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

Method for manufacturing asymmetric channel transistor

In order to form a self-aligned damascene gate with an attendant contact or contacts, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annealed. This dielectric layer is polished for planarity, a combined gate and contact mask is used to pattern the dielectric, and the interlayer dielectric is etched and the resist is stripped. The gate dielectric is deposited and polysilicon is then deposited over the dielectric and doped by implantation and then annealed. This polysilicon layer is polished to the dielectric level. The wafer is then masked to cover the gate and the polysilicon is anisotropically etched off in the contact areas. The exposed polysilicon at the gate site and the silicon exposed at the contact site are then salicided.

Self-aligned damascene gate with contact formation

The present invention provides a method for forming a MOS device having self-compensating threshold adjust implants and reduced junction capacitance. A semiconductor substrate of a first conductivity type is provided. A gate oxide is formed on the surface of the semiconductor substrate, and a polysilicon gate is formed on the surface of the gate oxide. A first implant of a dopant of the first conductivity type is performed so as to form self-compensating implant regions in the semiconductor substrate on opposite sides of the gate. Disposable sidewall spacers are then formed around the polysilicon gate. A second implant of a dopant of a second conductivity type is performed so as to create highly-doped source/drain regions which are self-aligned to the sidewall spacers. The substrate with self-compensating implant regions and the highly-doped source/drain regions is then subject to a rapid thermal anneal (RTA) process so as to activate the dopant in the self-compensating implant regions and the highly-doped source/drain regions. The dopant within the self-compensating regions diffuses laterally under the polysilicon gate to define pockets. Thereafter, the disposable sidewall spacers are removed. Finally, a third implant of a dopant of the second conductivity type is performed so as to create lightly-doped source/drain regions in the self-compensating implant regions on opposite sides of the gate.

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San Francisco, CA, United States of America

Richard P Rouse