Infineon Technologies Ag

Richard Lindsay

Manfred Eller

Henning Haffner

Frank Huebinger

Matthias Hierlemann

Jiang Yan

Martin Ostermayr

Klaus Schruefer

Cornelius Christian Russ

Yong Meng Lee

Sun-Oo Kim

David Alvarez

Sunoo Kim

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Integrated circuits and methods of design and manufacture thereof

A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Silicided semiconductor structure and method of forming the same

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Buried gate transistor

Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.

Capacitors and methods of manufacture thereof

A method of making a semiconductor device is disclosed. An upper surface of a semiconductor body is amorphized and a liner is formed over the amorphized upper surface. The upper surface can then be annealed. A transistor is formed at the upper surface.

Strained semiconductor device and method of making same

To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can then be removed and an electronic component (e.g., a transistor) that includes a feature (e.g., a gate) formed from the electrode layer can be formed.

An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration. A second source/drain region is also formed at the upper surface of the semiconductor body adjacent to a second edge of the gate, wherein the second source/drain region is doped with a dopant of the second conductivity type.

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Fishkill, NY, United States of America

Richard Lindsay