General Electric Company

Lockheed Martin Corporation

United States of America As Represented by the Secretary of the Air Force

Martin Marietta Corporation

Richard J Saia

Kevin Matthew Durocher

Mario Ghezzo

Bernard Gorowitz

Christopher James Kapusta

Paul Alan McConnelee

Robert F Kwasnick

Herbert S Cole

Thomas Bert Gorczyca

Bharat S Bagepalli

Dale M Brown

Ernest Wayne Balch

Vikram Bidare Krishnamurthy

James Wilson Rose

Raymond Albert Fillion

William Andrew Hennessy

Matthew Christian Nielsen

Imdad Imam

Dennis L Polla

Leonard Richard Douglas

James William Kretchmer

Ronald Frank Kolc

John Adam Edmond

Robert J Wojnarowski

Anil Raj Duggal

John Williams Palmour

George E Possin

Ching-Yeu Wei

Stephen Daley Arthur

David Joseph Najewicz

Manjin J Kim

Zachary Matthew Stum

Donald Paul Cunningham

Tat-Sing P Chow

Brian W Giambattista

Simon S Cohen

David E Holden

Charles Gerard Woychik

Mehmet Arik

Stanton Earl Weaver, Jr

Charles Erklin Seeley

Kanakasabapathi Subramanian

Joseph Alfred Iannotti

Peter Almern Losee

Alexander Viktorovich Bolotnikov

Donald Franklin Foust

Kevin Sean Matocha

Glenn Scott Claydon

Eladio Clemente Delgado

Ljubisa Dragoljub Stevanovic

Samhita Dasgupta

Anis Zribi

James Enrico Sabatini

Thomas Paul Feist

Jeffrey Bernard Fortin

Jack D Kingsley

Aaron Jay Knobloch

Christopher P Yakymyshyn

Kuna Venkat Satya Rama Kishore

Larry Gene Turner

Nicholas Okruch, Jr

Waseem A Roshen

William Gregg Hawkins

Roger S Ehle

Guanghua (George) Wu

Gregory Keith Dudoff

James Howard Schermerhorn

Piet Moeleker

Roger Raymond Kovalec

The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

Tapered gate electrode for semiconductor devices

A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.

Stress resistant micro-via structure for flexible circuits

A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0&#xd7;10per cm.

Semiconductor device with junction termination extension

Present embodiments are directed to an adhesive and method for assembling a chip package. The adhesive may be used to couple a chip to a substrate, and the adhesive may include an epoxy-based dielectric material, an epoxy resin, a photoacid generator, an antioxidant, and a cold catalyst corresponding to the photoacid generator.

Chip attach adhesive to facilitate embedded chip build up and related systems and methods

An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer.

Interconnect structure

An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.

Apparatus and method for reducing pitch in an integrated circuit

An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.

Electronic chip package with reduced contact pad pitch

A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

System and method of forming a wafer scale package

A method of manufacturing an ignition device is provided. The method includes patterning a plurality of resistors on a membrane to form heating elements and thermally isolating the heating elements from an external environment via a cavity disposed adjacent to the heating elements.

Method of making an ignition device

A system and method for providing shielding to an electrical system is disclosed. A conformal shield is formed by applying a conformal insulating coating to an electrical system. A plurality of openings are formed in the insulating coating at desired locations and a first metallic layer is deposited over the insulating coating and in each of the plurality of openings, the first metallic layer being electrically connected with the circuit board at the desired locations. A second metallic layer is then deposited onto the first metallic layer to increase a thickness of the metallic layers.

System and method of forming a low profile conformal shield

A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

Techniques for fabricating a resistor on a flexible base material

Large, light-weight organic devices and methods of preparing large, light-weight organic devices. Specifically, flexible and rigid light-weight plastics are implemented. The flexible plastic may be disposed from a reel. A metal grid is fabricated on the flexible plastic to provide current conduction over the large area. A transparent oxide layer is provided over the metal grid to form the bottom electrode of the organic device. A light emitting or light gathering organic layer is disposed on the transparent oxide layer. A second electrode is disposed over the organic layer. Electrodes are coupled to the metal grid and the second electrode to provide electrical current to or from the organic layer. Depending on the type of materials used for the organic layer, the organic device may comprise an area light device or a photovoltaic device.

Large organic devices and methods of fabricating large organic devices

A mechanism and a method for framing a low-distortion flexible dielectric substrate during subsequent flex circuit processing. The processing method comprising the following steps: making a flexible dielectric substrate having an outer periphery; joining a continuous portion of the flexible dielectric substrate near the outer periphery to a rigid open frame, the flexible dielectric substrate being in a state other than a state of substantially uniform tension as a result of the joinder; causing the joined flexible dielectric substrate to undergo a change to the state of substantially uniform tension; and printing an electrical conductor on the flexible dielectric substrate while the flexible dielectric substrate is joined to the frame and in the state of substantially uniform tension. The frame is in the shape of a polygon (e.g., a rectangle) with rounded vertices.

Method of processing high-resolution flex circuits with low distortion

A piezoelectric microvalve and method for controlling a fluid flow through a piezoelectric microvalve are provided. The microvalve includes an inlet plenum and a flow directing structure for directing a fluid flow, wherein a first side of the structure is in fluid communication with the inlet plenum. The microvalve also includes a piezoelectric bending actuator comprising a flap portion responsive to a command signal for controlling a fluid flow through the flow directing structure. The microvalve further includes an outlet plenum in fluid communication with a second side of the flow directing structure.

Piezoelectric microvalve

An optoelectronic package is fabricated by a method which includes: positioning an optical device within a window of a substrate active-side up and below a top substrate surface; filling the window with an optical polymer material; planarizing surfaces of the optical polymer material and the substrate; patterning waveguide material over the optical polymer material and the substrate to form an optical interconnection path; and to form a mirror to reflect light from the optical device to the interconnection path; and forming a via to expose a bond pad of the optical device.

Optoelectronic package and fabrication method

Growing community of inventors

Schenectady, NY, United States of America

Richard J Saia