Digital Equipment Corporation

Richard J Casabona

Robert E Stewart

David P Rodgers

John V Levy

David Martin Fenwick

William D Strecker

Charles R Barker, Iii

David Thompson

David Potter

A package for integrated circuit chips, or other electrical devices, provides mechanical shock and thermal protection for the chips, and in addition, protects the chips from electromagnetic interference and electrostatic discharge. The package includes a printed wiring board base for reception of one or more circuit chips, and a conductive heat sink and cover. The conductive heat sink, in conjunction with a reference plane in the wiring board base, acts as an EMI shield for the chips. The heat sink is covered with an insulating layer, on top of which, a conductive coating is placed. The conductive coating is electrically connected to the reference plane, and the two act to protect the chips from electrostatic discharges. Compliant pads support the chips, and a thermally conductive elastomer can be placed on top of each chip between the chips and the inner top surface of the heat sink. The chips are thereby held securely in position, and are thermally connected to the heat sink.

Package for EMI, ESD, thermal, and mechanical shock protection of

A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.

Dual path bus structure for computer interconnection

A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, as a commanding nexus, seeks control of the interconnection and then transmits a command and address of a storage location in the other element when it receives control of the interconnection. Control is then relinquished unless the one element is to send data to the other element whereupon the data is sent immediately. If data is to be retrieved, the other element retrieves the data, requests control of the interconnection and, when it receives control, transmits the data onto the interconnection with an identification of the one element. The one element then retrieves the data from the interconnection when it recognizes its own identification. If the other element is a memory element, it also contains storage file for storing commands and data if it already is operating in response to another element's command.

Data processing system with read operation splitting

Bus for a data processing system with overlapped sequences

A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses on a priority basis. A central clocking circuit generates timing signals that control such communications by defining bus cycles on a synchronous basis and each nexus contains priority circuitry that operates in response to these signals. Each nexus that requires access to the interconnection asserts a transfer request signal at a predetermined time during each bus cycle. Priority arbitration circuitry in each nexus receives all such requests and samples them at another, later, time during each bus cycle. When a nexus is transmitting a request and no nexus with a higher priority is transmitting a request, that nexus takes control of the interconnection. A transfer during a subsequent bus cycle to another nexus can be prevented during certain types of transfers.

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Stow, MA, United States of America

Richard J Casabona