Taiwan Semiconductor Manufacturing Comp. Ltd.

Amberwave Systems Corporation

Qualcomm Incorporated

Iqe Plc

Agency for Science, Technology and Research

Richard Hammond

Matthew T Currie

Eugene A Fitzgerald

Anthony J Lochtefeld

Thomas A Langdo

Glyn Braithwaite

Andrew C Clark

Rodney Pelzel

Stephen Alan Fanelli

Shiqun Gu

Sinan Goktepeli

Rytis Dargis

Michael S Lebby

Michael Andrew Stuber

Ranadeep Dutta

Narayanan Balasubramanian

Plamen Vassilev Kolev

Steve Fanelli

Francesco Carobolante

Matthew Michael Nowak

Gengming Tao

Drew Nelson

Alan Gott

Clark Andrew

Michael Lebby

David Cheskis

Layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.

Electronic device with 2-dimensional electron gas between polar-oriented rare-earth oxide layer grown over a semiconductor

A layered structure () for transmission of an acoustic wave, the layered structure () comprising: a substrate layer (); and a second layer () over the substrate layer (), wherein the second layer () comprises a plurality of discrete portions () adjacent to each other, each discrete portion () of the plurality of discrete portions () comprising a first subregion (A) and a second subregion (B). Also an epitaxial layer (), grown over the second layer (), for transmission of the acoustic wave in a major plane of the epitaxial layer (), wherein a periodicity (&#x3bb;) of a wavelength of the acoustic wave to be transmitted through the epitaxial layer () is approximately equal to a sum of a width (d) of the first subregion (A) and a width (d) of the second subregion (B).

Localized strain fields in epitaxial layer over cREO

Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.

Integrated epitaxial metal electrodes

Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region, a collector region, and a base region disposed between the emitter region and the collector region, the base region and the collector region comprising different semiconductor materials. The HBT device may also include an etch stop layer disposed between the collector region and the base region. The HBT device also includes an emitter contact, wherein the emitter region is between the emitter contact and the base region, and a collector contact, wherein the collector region is between the collector contact and the base region.

Self-aligned collector heterojunction bipolar transistor (HBT)

A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein.

Semiconductor material having tunable permittivity and tunable thermal conductivity

An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

Porous semiconductor handle substrate

A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.

Porous silicon dicing

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Reacted conductive gate electrodes and methods of making the same

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Methods of forming strained-semiconductor-on-insulator device structures

The structures and methods disclosed herein include changing composition of a metal alloy layer in an epitaxial electrode material to achieve tunable work functions for the electrode. In one example, the tunable work function is achieved using a layered structure, in which a crystalline rare earth oxide (REO) layer is epitaxially over a substrate or semiconductor, and a metal layer is over the crystalline REO layer. A semiconductor layer is thus in turn epitaxially grown over the metal layer, with a metal alloy layer over the semiconductor layer such that the ratio of constituents in the metal alloy is used to tune the work function of the metal layer.

Metal electrode with tunable work functions

An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

Utilization of backside silicidation to form dual side contacted capacitor

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or 'FETs') that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

CMOS and bipolar device integration including a tunable capacitor

A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.

Porous silicon post processing

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.

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Harriseahead, United Kingdom

Richard Hammond