International Business Machines Corporation

Richard Glen Southwick, Iii

Choonghyun Lee

Hemanth Jagannathan

Xin Miao

Alexander Reznicek

Zuoguang Liu

Chun Wing Yeung

A method of forming a vertical transport field-effect transistor (VFET) is provided. The method includes forming vertical fin channels by etching part way through a substrate. The method further includes forming a bottom source/drain electrode partially into the substrate and beneath the vertical fin channels. A gate dielectric layer is then formed on the vertical fin channels. A gate conductor layer is then formed on the gate dielectric layer. A height of the gate conductor layer is less than a height of the vertical fin channels. The method further includes forming a spacer layer on a top surface of the gate conductor layer. The method also includes forming a top source/drain electrode on a top surface of the vertical fin channels. A gap exists between the top source/drain electrode and the spacer layer.

Vertical field effect transistor and method of manufacturing a vertical field effect transistor

Semiconductor device structures and techniques are provided for measuring contact resistance. A semiconductor device is disclosed including a first source/drain region and a contact disposed on the first source/drain region and configured to supply energy to the semiconductor device. A fin extends between the first source/drain region and a second source/drain region of the semiconductor device. A first contact material layer is disposed on the second source/drain region and a first active drain contact is disposed on the first contact material layer. A first sensor drain contact is also disposed on the first contact material layer. A second contact material layer is disposed on the second source/drain region and a second active drain contact is disposed on the second contact material layer. A third contact material layer is disposed on the second source/drain region and a second sensor drain contact is disposed on the third contact material layer.

Measurement of top contact resistance in vertical field-effect transistor devices

A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.

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Halfmoon, NY, United States of America

Richard Glen Southwick, Iii