International Business Machines Corporation

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Novellus Systems Incorporated

Tokyo Electron Limited

Samsung Electronics Co., Ltd.

Applied Materials, Inc.

Morton International, Inc.

Richard Anthony Conti

Jonathan Daniel Chapple-Sokol

Son Van Nguyen

Jeffrey P Gambino

Michael P Belyansky

James Anthony O'Neill

Laertis Economikos

Steven G Barbee

Ashima B Chakravarti

Daewon Yang

Daniel C Edelstein

Eric R Miller

David M Dobuzinsky

Katherina E Babich

Jay William Strane

Jeffrey C Shearer

Jessica M Dechene

Gill Yong Lee

Peter D Hoh

Justin W Wong

Kangguo Cheng

Nicolas J Loubet

Oleg Gluschenkov

Fee Li Lie

Yun-Yu Wang

Chandrasekhar Narayan

Kwong Hon Wong

David Edward Kotecki

Huimei Zhou

Anita Madan

Devendra K Sadana

Choonghyun Lee

Ramachandra Divakaruni

Dechao Guo

Balasubramanian Pranatharthiharan

Zhenxing Bi

Marie Angelopoulos

Rolf Weis

Dirk Pfeiffer

Richard Hsiao

Gary Bela Bronner

Donald Francis Canaperi

Sean David Burns

Jochen C Beintner

Wesley Charles Natzle

George D Papasouliotis

James John Kelly

David L O'Meara

Scott David Halle

Wolfgang Bergner

Anthony Dip

Allen H Gabor

Seshadri Subbanna

Todd Christopher Bailey

Arpan Pravin Mahorowala

Pao-Hwa Chou

Alexander William Simpson

Aelan Mosden

Thomas J Haigh, Jr

Badih El-Kareh

Yi Song

Andreas Knorr

Mary Elizabeth Weybright

Uwe Schroeder

Donna Rizzone Cote

Jyothi Singh

Ruilong Xie

Juntao Li

Xin Miao

Shogo Mochizuki

Keith Kwong Hon Wong

Li-Qun Xia

Ellie Y Yieh

Robert Russell Robison

Andrew Mark Greene

Su Chen Fan

Andrew Herbert Simon

Ravikumar Ramachandran

John Anthony Fitzsimmons

Renee Tong Mo

Muthumanickam Sankarapandian

David Lee Rath

Paul Charles Jamison

Michael Jay Shapiro

Kathryn Turner Schonenberg

Patrick A Van Cleemput

Michael F Lofaro

James F White

Michael D Armacost

Darryl D Restaino

Byeongju Park

Jeremy K Stephens

Zhao Lun

Johnny Widodo

Axel Christoph Brintzinger

Manu J Tejwani

William C Wille

Kenneth M Davis

Rashmi Jha

Chester T Dziobkowski

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Stressed material within gate cut region

A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

Nano multilayer carbon-rich low-k spacer

A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.

Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer

A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.

Dual width finned semiconductor structure

Provided are embodiments of a method for forming a semiconductor device. The method includes forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises channel layers and nanosheet layers, forming a sacrificial gate over the nanosheet stack, and forming trenches to expose sidewalls of the nanosheet stack. The method also includes forming source/drain (S/D) regions, where forming the S/D regions including forming first portions of the S/D regions on portions of the nano sheet stack, forming second portions of the S/D regions, wherein the first portions are different than the second portions, and replacing the sacrificial gate with a conductive gate material. Also provided are embodiments of a semiconductor device formed by the method described herein.

Nanosheet transistor having a strained channel with strain-preserving multi-segmented source/drain regions

Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.

Middle-of-line interconnect having low metal-to-metal interface resistance

A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.

Self-aligned gate contact integration with metal resistor

Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

Stress modulation of nFET and pFET fin structures

Highly selective dry etching techniques for VFET STI recess are provided. In one aspect, a method for dry etching includes: contacting a wafer including an oxide with at least one etch gas under conditions sufficient to etch the oxide at a rate of less than about 30 &#x212b;/min; removing a byproduct of the etch from the wafer using a thermal treatment; and repeating the contacting step followed by the removing step multiple times until a desired recess of the oxide has been achieved. A method of forming a VFET device is also provided.

Highly selective dry etch process for vertical FET STI recess

An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.

Multi-level air gap formation in dual-damascene structure

A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.

Protection of low temperature isolation fill

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Richard Anthony Conti