Texas Instruments Corporation

Ramtron International Corporation

Other

Nippon Steel Semiconductor Corporation

Richard Allen Bailey

John Anthony Rodriguez

Carl Z Zhou

Archana Venugopal

Jarrod Eliason

E Henry Stevens

Glen Richard Fox

Robert Christopher Baumann

Michael Allen Ball

Sunil Kumar Dusa

Thomas C Taylor

Scott Robert Summerfelt

Douglas Blaine Butler

Kemal Tamer San

Huang-Chun Wen

Antonio Guillermo Acosta

Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

Low-temperature passivation of ferroelectric integrated circuits for enhanced polarization performance

A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.

Physical unclonable function system and method

A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.

Screening for data retention loss in ferroelectric memories

A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

Fusible link cell with dual bit storage

Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all 1's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

Random number generation in ferroelectric random access memory (FRAM)

Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all l's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined for each integrated circuit being tested, corresponding to the read of a high polarization capacitance data state. A number of FRAM cells in the integrated circuit are programmed to that data state, and then read at an elevated temperature, with the number of failing cells compared against a pass/fail threshold to determine whether the integrated circuit is vulnerable to long-term data retention failure.

Reliability screening of ferroelectric memories in integrated circuits

A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A 'shmoo' of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.

Screening for later life stuck bits in ferroelectric memories

Ferroelectric memory cells () are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell () is not being accessed while avoiding significant disruption of memory cell access operations. Methods () are provided for fabricating ferroelectric memory cells () and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material () or in an encapsulation layer () formed over the patterned capacitor structure (C).

Ferroelectric capacitor with parallel resistance for ferroelectric memory

The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising ferroelectric capacitors (). A short delay polarization value is obtained () by writing a data value, performing a short delay, and reading the data value. A long delay polarization value is obtained () by again writing the data value, performing a long delay, and again reading the data value. The short delay and long delay polarization values are compared () to obtain a data retention lifetime for the ferroelectric memory device. The obtained data retention lifetime is compared with acceptable values () and, if deemed unacceptable, avoids unnecessary performance of thermal bake data retention lifetime testing.

Process monitoring for ferroelectric memory devices with in-line retention test

A hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in non-volatile integrated circuit memory devices. The resultant device structure ameliorates the hydrogen induced degradation of ferroelectric capacitors by completely encapsulating the capacitor within a suitable hydrogen barrier material, such as chemical vapor deposition (&ldquo;CVD&rdquo;) or sputtered silicon nitride, thus ensuring process compatibility with industry standard process steps. Although the deposition process for CVD Si N itself contains hydrogen, the deposition time may be kept relatively short thereby allowing the TiN local interconnect layer to act as a &ldquo;short term&rdquo; hydrogen barrier. The techniques of the present invention are applicable to all known ferroelectric dielectrics including Perovskites and layered Perovskites (whether doped or undoped) including PZT, PLZT, BST, SBT and others while simultaneously allowing for a potentially broader choice of electrode materials and the use of a forming gas anneal process step on the completed IC structure.

HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES

A cable storage device for providing a storage for cable. The cable storage device includes a housing assembly including a housing member; and also includes a handle member being attached to an exterior of the housing member; and further includes a spool member being rotatably disposed in the housing member and being adapted to carry a cable; and also includes a crank member being attached to the spool member for turning the spool member to take up the cable; and further includes bracket members being securely attached to the housing member and being adapted to support an end portion of the cable.

Growing community of inventors

Richardson, TX, United States of America

Richard Allen Bailey