International Business Machines Corporation

Globalfoundries Inc.

Richard A Phelps

Robert Mark Rassel

Michael Joseph Zierak

James Albert Slinkman

Yun Shi

John J Ellis-Monaghan

Alan Bernard Botula

Alvin Jose Joseph

Renata A Camillo-Castillo

Randy Lee Wolf

Robert J Gauthier, Jr

Max Gerald Levy

Mark David Jaffe

Xuefeng Liu

Natalie Barbara Feilchenfeld

Anthony K Stamper

Andreas Daniel Stricker

Ephrem G Gebreselasie

Erik Mattias Dahlstrom

Frederick Gustav Anderson

Xiaowei Tian

Jeffrey P Gambino

Steven H Voldman

Steven M Shank

Jed Hickory Rankin

Andres Bryant

James William Adkisson

Jerome Brett Lasky

John B Campi, Jr

David S Collins

David L Harmon

BethAnn Rainey

Joseph R Greco

Santosh Sharma

David A DeMuynck

Jennifer C Robbins

John E Dillon

Kevin C Remillard

Kevin Munger

William Savaria

Ross Duncan

Terence B Hook

Zhong-Xiang He

Jeffrey Bowman Johnson

Siva P Adusumilli

John Joseph Pekarik

William F Clark, Jr

Ebenezer E Eshun

Michel J Abou-Khalil

Theodore James Letavic

Stephen Arthur St Onge

Martin Knaipp

Panglijen Candra

Gerd Pfeiffer

Rainer Minixhofer

Georg Roehrer

Charles Arthur Whiting

Michael J Hauser

Hubert Enichlmair

Ian McCallum-Cook

Douglas Brian Hershberger

Eric D Johnson

Blaine Jeffrey Gross

Kenneth F McAvey

Bernard Loeffler

Jong-Mun Park

Dennis L Macaluso

Michael L Zierak

Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

Shallow trench isolation formation without planarization

Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

SOI-MOSFET gate insulation layer with different thickness

The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The structure includes: a transistor formed over a semiconductor material and an underlying substrate; and multiple isolated contact regions under a body or channel of the transistor, structured to provide a local potential to the body of the transistor at different locations.

Multiple back gate transistor

Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.

Air gaps formed by porous silicon removal

Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Dual shallow trench isolation (STI) structure for field effect transistor (FET)

A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants.

High resistivity substrate final resistance test structure

High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.

High voltage laterally diffused metal oxide semiconductor

A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage

Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Silicon controlled rectifier with stress-enhanced adjustable trigger voltage

Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure

A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.

Compensation for a charge in a silicon substrate

Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

Back-end-of-line metal-oxide-semiconductor varactors

Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (V) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vof the diode (e.g., increasing the length reduces Vof the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode

A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce R. A related method and design structure are also disclosed.

Asymmetric wedge JFET, related method and design structure

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Colchester, VT, United States of America

Richard A Phelps